Fig. 6: Stability of the three-dimensional (3D) ternary logic inverter (T-inverter). | Nature Communications

Fig. 6: Stability of the three-dimensional (3D) ternary logic inverter (T-inverter).

From: Vertically stacked, low-voltage organic ternary logic circuits including nonvolatile floating-gate memory transistors

Fig. 6

a The change in transfer characteristics of the flash memory according to time after the optimum programming state (programming voltage (Vprg) =  + 19 V) and b drain current (ID) at gate voltage (VG) = 1 V and ID = 2 V versus time in the programming (open symbol) and erasing (closed symbol) states. c The comparison of the retention characteristics and programming voltage/erasing voltage (Vprg/Vers) of the flash memory in this study to those based on polymer dielectrics in the previous reports. d The change in transfer curves of the flash memory according to time and the transfer curve of the heterojunction transistor (HTR). e The change in voltage transfer characteristics (VTCs) and f intermediate logic value of the 3-dimensional (3D) ternary logic inverter (T-inverter) according to time. g The VTCs of 100 consecutive sweeps of the 3D T-inverter with the optimum programming states, and h output voltage (VOUT) values at input voltage (VIN) = 0, 3.25, and 5 V extracted from each cycle.

Back to article page