Fig. 4: Dynamic response of the MoS2 memristor for memory-based computing.
From: Wafer-scale solution-processed 2D material analog resistive memory array for memory-based computing
a AC endurance obtained with 1 μs pulse width (1.5 V for set, and -2.0 V for reset). b Statistical distribution of the set/reset voltages for 73 devices measured over the entire wafer. The inset is the MoS2 memristors on a 2-inch wafer. c Potentiation and depression of MoS2 memristor by sequence of pulse train showing high analog on/off conductance ratio. d I-t measured at 0.2 V after sequentially resetting the MoS2 memristors into 10 memory states. e Conductance update as a function of incremental potentiation and depression pulse numbers. f Comparison of classification accuracy of a 3-layer CNN executed in-memory with GPU execution over 100 epochs. GPU execution achieved 98.24% accuracy while proposed technique achieved a similar accuracy 98.02%. g A 3-layer DCNN with 1 convolutional and 2 fully-connected layers used to classify handwritten digits. The convolution layer consists of 5 7 × 7 filters while the hidden node in the fully connected layers has 30 neurons. Notably, MoS2 memristor with flake size of 0.48 um was examined in this section.
