Fig. 5: Demonstration of 3D stacked 2D MoS2 memristors.
From: Wafer-scale solution-processed 2D material analog resistive memory array for memory-based computing
Cross-sectional TEM images of the full stack (a) and middle layer (b) of MoS2 memristor. c Elemental mapping of the 3D stacked MoS2 memristor. d I-V characteristics of 3D stacked MoS2 memristors, showing stable and bipolar resistive switching at each layer. e Schematic diagram of 3D memristor array with buried metal interconnects and logic circuits.
