Fig. 4: Reconfigurable OR logic gate. | Nature Communications

Fig. 4: Reconfigurable OR logic gate.

From: Ferroelectric domain-wall logic units

Fig. 4: Reconfigurable OR logic gate.

a–c CDW networks at the initial state and controlled by an in-plane trailing field in a BiFeO3 nano-island with an AR of 1.25. The connection/disconnection of \({A}^{{\prime} }\)/\({B}^{{\prime} }\) node and disconnection/connection of \({C}^{{\prime} }\)/\({D}^{{\prime} }\) node is implemented concurrently in one nano-island by applying an in-plane field along [\(\bar{1}\bar{1}0\)] (b) or [\(110\)] direction (c). d–g c-AFM images and corresponding logic circuit diagrams of two series-connected nano-islands with the sequence of logic operations for inputs of ‘11’, ‘10’, ‘01’, and ‘00’. h Truth table for OR logic gate respectively. E1 and E2 are the applied  in-plane trailing fields for the two nano-islands. R represents the resistance of the DW between the output electrodes.

Back to article page