Fig. 2: Sample characterizations and electrical properties of CFO nanosheets.

HRTEM image (a), SAED pattern (b) and TEM-EDS elemental mapping images (c) of ultrathin CFO nanosheets. Here the lattice spacing is measured to be 0.298 nm, corresponding to its (2\(\bar{2}\)0) planes. d Raman spectrum of CFO nanosheet transferred onto silicon substrate. e Polarimetric SHG pattern obtained by rotating the CFO nanosheet while fixing the polarization of incident laser and collection analyzer. The solid line is the fitting curve. f I_DS–V_DS curves of an 11.5 nm-thick CFO device measured at different temperatures from 300 K to 100 K with a 10 K step. Inset: The corresponding in-situ device schematic on mica substrate. g The Arrhenius plot of conductance (G) gives a thermal activation energy (E_a) of 44.1 meV. Inset: Plot of E_a along with channel thickness. h I_DS–V_DS curves of a 23 nm-thick CFO vertical device, showing switchable behavior. Sweep directions are indicated by arrows. Inset: Device schematic of CFO vertical device.