Fig. 3: 2D memtransistor-based s-bit generator.
From: Hardware implementation of Bayesian network based on two-dimensional memtransistors
a Transfer characteristics of a representative 2D memtransistor measured after the application of 100 cycles of \({V}_{P}\) = −10 V (dark green) and \({V}_{E}\) = 10 V (light green) pulses, each for \({\tau }_{s}\) = 100 μs. Distribution of b post-programmed and c post-erased conductance states (\({G}_{{MT}}\)) measured using \({V}_{{BG}}\) = 0 V. d Circuit diagram and e corresponding optical image for the proposed s-bit generator consisting of six memtransistors (\({MT}1\), \({MT}2\), \({MT}3\), \({MT}4\), \({MT}5\), \({MT}6\)). f Voltage waveforms applied to nodes \(N1\) and \(N2\), i.e., \({{{{{{\rm{V}}}}}}}_{N1}\) and \({{{{{{\rm{V}}}}}}}_{N2}\). During each clock cycle (\({\tau }_{{clk}}\)), \({V}_{N1}\) toggles between 0 V, 0 V, and \({V}_{{DD}}\) = 2 V and \({V}_{N2}\) toggles between \({V}_{P}\) = −7 V, \({V}_{E}\) = 10 V, and \({V}_{R}\) = 1 V. Voltages applied to nodes \(N3\) and \(N4\), i.e., \({V}_{N3}\) and \({V}_{N4}\), are held constant at 1 V and 0 V, respectively. g Voltage readout at node \(N5\), i.e., \({V}_{N5}\). h Distribution of \({V}_{N5}\) over 200 \({\tau }_{{clk}}\) follows a random Gaussian distribution with a mean (\({\mu }_{{VN}5}\)) of 0.40 V and a standard deviation (\({\sigma }_{{VN}5}\)) of 0.02 V. i Output, \({V}_{N6}\), of an inverting amplifier constructed using \({MT}3\) and \({MT}4\) as a function of the input, \({V}_{N5}\), with a gain of ~24. j \({V}_{N6}\) corresponding to \({V}_{N5}\) shown in g. k Distribution of \({V}_{N6}\) follows a random Gaussian distribution with a mean (\({\mu }_{{VN}5}\)) of 0.99 V and a standard deviation (\({\sigma }_{{VN}5}\)) of 0.41 V. l Output, \({V}_{N7}\), of a thresholding inverter constructed using \({MT}5\) and \({MT}6\) as a function of the input, \({V}_{N6}\), for different inversion threshold, \({V}_{{IT}}\). m \({V}_{N7}\) corresponding to \({V}_{N6}\) shown in i for different \({V}_{{IT}}\). n Probability of obtaining ‘1’ in the bit-stream (\({p}_{s}\)) as a function of \({{{{{{\rm{V}}}}}}}_{{{{{{\rm{IT}}}}}}}\).
