Fig. 4: Hardware implementation of BN.

a Circuit schematic for hardware implementation of a BN using three s-bit generators and one 2×1 MUX\(.\) The \({MUX}\) consists of one inverter and three 2-input \({NAND}\) gates. b Optical image and corresponding circuit configuration of a 2-input \({NAND}\) gate comprising 3 memtransistors (\({MT}1\), \({MT}2\), and \({MT}3\)) connected in series, with \({MT}1\) serving as the depletion load. c Input waveforms, \({V}_{N3}\) and \({V}_{N4}\), which are applied to the local back-gate terminals of \({MT}2\) and \({MT}3\) at nodes \({N}_{3}\) and \({N}_{4}\), respectively, and the corresponding output waveform, \({{{{{{\rm{V}}}}}}}_{{{{{{\rm{N}}}}}}2}\), which is obtained at node \({N}_{2}\). d Optical image and e corresponding circuit configuration for hardware implementation of a 2-node BN consisting of 3 s-bit generators and a 2×1 \({MUX}\) for a total of 29 memtransistors. The \({V}_{{IT}}\) values for the s-bit generators for \({X}_{1}\) and \({X}_{2}\) can be pre-programmed using the CPT for the nodes \({{{{{\rm{A}}}}}}\) and \({{{{{\rm{B}}}}}}\). f Representative stochastic bit-streams for the random variables \(A\), \({X}_{1}\), and \({X}_{2}\) with \(P\left(A\right)\) = 0.28, \(P\left({X}_{1}\right)\) = \({{{{{\rm{P}}}}}}\left({{{{{\rm{B}}}}}}/{{{{{\rm{A}}}}}}\right)\) = 0.50, and \(P\left({X}_{2}\right)\) = \(P\left(B/{A}^{C}\right)\) = 0.56. g Correlation coefficient (\({CC}\)) values between \(A\), \({X}_{1}\), and \({X}_{2}\) confirm mutual independence of the s-bit generator modules. h Stochastic bit-streams obtained at the output node, \(B\). The measured and expected values for \(P\left(B\right)\) are 0.56 and 0.54, respectively.