Table 1 Comparison of various hardware implementations of spiking neurons

From: Compact artificial neuron based on anti-ferroelectric transistor

Mechanism

Variation#

Structure

Endurance

Energy/spike

Hardware

Self-reset

Driven capability

Redox

9.63%–31.4%10,48,49,50,51

SiOxNy:Ag10

>106

>60 pJ*

1 C + 1 T + 1ED

x

Ag/SiO211

>108

~500 nJ*

1 C + 2 T + 1ED

x

Ag/HfO213

——

18 pJ

1 C + 1 T + 1ED

x

Mott

6.31%–11.9%17,52,53,54

NbO213

——

~52 pJ

1 C + 1 T + 1ED

x

NbOx14

>1012

~3 pJ*

1 T + 1ED

x

GaTa4Se818

——

~10 uJ*

1 T + 1ED

x

Phase-change

6.82%–12.5%20,55

GST20

3 × 109

>50 pJ

19 T + 1ED

x

GST22

——

10 pJ*

>1 C + 7 T + 1ED

x

Magnetic

3%–10%56,57,58

MTJ23

——

~7 fJ (simulation)

>4 T + 2ED

x

STT-MRAM24

——

——

>21 T + 1ED

x

Ferroelectric

1%– 4.03%32,59,60

FeFET30

——

~360 pJ (simulation)

3 C + 9 T + 1ED

x

FeFET29

——

1–10 pJ

1 C + 6 T + 1ED

x

Leaky-FeFET32

——

~420 pJ*

2 T + 1ED

x

Anti-ferroelectric

<3.93%**

AFeFET

>1012

37 fJ

8 T + 1ED

  1. #The variation results are rarely reported in literature. In this table, the variation data are obtained from devices with the same mechanism category.
  2. *The energy consumption per spike is calculated approximately from the It and Vt curves in these reference papers, respectively.
  3. **With further optimizing the stimuli pulse parameters.
  4. √ has this property.
  5. x has no such property.
  6. To unify the benchmark of hardware overhead, all the circuit components in these reference papers are equivalent to three categories: capacitor (C), emerging device (ED) and transistor (T). In chip manufacturing, the area of a resistor is equivalent to that of a transistor. 1 latch is composed of four transistors. 1 XOR gate is composed of ten transistors. An integrated operational amplifier usually consists of more than 20 transistors.