Fig. 4: Large-scale logic circuit made by vdWs dielectric integration method.
From: Wafer-scale high-κ dielectrics for two-dimensional circuits via van der Waals integration
a The output voltage (black line and left axis) versus input voltage Vin and voltage gain (red line and right axis) as a function of Vin of a NMOS inverter under Vdd~5 V. The corresponding optical image is shown as inset. b–d Output voltage and corresponding optical image (inset) of NAND gate (b), NOR gate (c) and AND gate (d) at for typical input voltage with drain supply voltage at 5 V. e, f Optical image (e) and output-input logic functions (f) of a monolayer MoS2 XOR gate. Vdd, drain supply voltage; Vin, input voltage; Vout, output voltage; INA: input A; INB: input B; GND: ground. The scale bars for all-optical images are 50 µm.
