Fig. 3: Clock jitter measurement results. | Nature Communications

Fig. 3: Clock jitter measurement results.

From: Femtosecond-precision electronic clock distribution in CMOS chips by injecting frequency comb-extracted photocurrent pulses

Fig. 3: Clock jitter measurement results.The alternative text for this image may have been generated using AI.

a Diagram of the test chip related to jitter measurement. Note that the output clock signal from C2 is used as the input clock signal of the H-tree. b Jitter measurement background. c–f Jitter histograms of the generated 1 GHz clocks were measured off-chip through an open-drain clock driver in the test chip. Standard deviation and peak-to-peak jitter values were extracted from 100,000-hit-count histograms of the signal crossing at half maximum level.

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