Fig. 3: Superlattice devices with GST467 nanocomposite and TiTe2 thermal barriers.
From: Novel nanocomposite-superlattices for low energy and high stability nanoscale phase-change memory
a Schematic of TiTe2/GST467 superlattice device, TiTe2 forming thermal barriers28 and GST467 as the phase-change layers. b XRD of TiTe2/GST467 superlattice (SL) on a TiN (20 nm thick)/Si substrate showing the polycrystallinity of the as-deposited SL. c Comparing the high-temperature stability of HRS in a TiTe2/GST467 superlattice device with a Sb2Te3/GST467 superlattice device and a GST467 control device (all with 40 nm BE diameter). The HRS of TiTe2/GST467 and control GST467 devices are similar, with no re-crystallization for >3 hours at 145 °C. Measurement protocols are described in Fig. 2f. Room temperature (RT) is 20 °C. d Effect of fall times on set transition for TiTe2/GST467 and control GST467 devices. Devices have 40 nm BE diameter, and all pulses have 1 ns rise time and 30 ns widths. Measurement protocols are described in Fig. 2d. Both device types show fast switching speed of ≈ 40 ns. e Effect of SL period thickness on device reset current, keeping SL thickness fixed ( ≈ 65 nm). We expect the GST467 layer to dominate the overall on/off ratio in the superlattice stack because TiTe2 itself has a small resistance on/off ratio47 (≈4). On the other hand, thinner GST467 layers lead to a reduction of reset current, as more internal interfaces enable better heat confinement30. f Effect of SL period thickness on device resistance on/off ratio. Low reset current and ≈ 100× resistance window are simultaneously achieved with the 2/4 nm/nm TiTe2/GST467 superlattice devices. g Scaling of reset current with BE diameter (from ≈ 40 to 80 nm) is maintained for TiTe2/GST467 superlattice devices. For reset programming (LRS to HRS), we used 1/20/1 ns pulses. h Endurance of our optimized 2/4 nm/nm TiTe2/GST467 superlattice PCM with 40 nm BE diameter (up to 2 × 108 cycles), while maintaining a resistance on/off ratio of ≈ 100.
