Fig. 1: M3D-LIME chip with hybrid memory architecture.
a Architecture of the M3D-LIME chip, which consists of three sequentially integrated layers. The 1st layer of Si CMOS logic is fabricated using a standard 130 nm CMOS process for control logic and data interface. The 2nd layer of CIM is fabricated with HfAlOx-based analog RRAM 1T1R arrays to perform MVM calculations of CNN for feature extraction. The 3rd layer of TCAM is fabricated with CNTFET and Ta2O5-based digital RRAM in the form of 2T2R arrays to implement template storing and matching as well as in the form of 1T1R on-chip buffer for the CIM layer. Both the 2nd and 3rd layers are fabricated using a carefully optimized BEOL-compatible process at a low temperature (≤300 oC) without affecting the pre-fabricated layers underneath. The left panels illustrate the implementation of one-shot/few-shot learning on the M3D-LIME chip. With the help of CMOS logic, feature extraction is implemented by the CIM and buffer arrays while template matching is performed on the TCAM array. b Cross-sectional TEM image of the fabricated M3D-LIME chip in this work, confirming the structural integrity of all three functional layers. Scale bar: 1 μm.
