Fig. 3: Overall hardware-based classification process.

For hardware-based classification, a 32 × 30 array, representing a partial array of the 1 kb CA, was utilized. To classify the three digits (0, 1, and 2), the 32 × 30 array is partitioned into 10 sets of 32 × 3 matrices. Each column in a submatrix (32 × 1) indicated the three digits 0, 1, and 2. a The training and test (inference) datasets were processed by software simulation. By downscaling the MNIST data, originally consisting of 28 × 28 pixels, to 20 × 16 pixels to fit into the 32 × 30 array. To input the images into array for training and inference tasks, the down-sampled images were converted to 320 × 1 matrix and partitioned into 10 sets of 32 × 1 matrices. The training process was performed using the resized data in the software, and the trained data were converted into target conductance (resistance) values to obtain the distribution of trained weights. Based on these weight values, each cell in the 32 × 30 CA was programmed. b For the inferencing operations, the resized data were converted into 320 × 1 input vectors with binary values of 0 and 1. These input vectors were then converted into voltages and applied to the memristor matrix in 10 sets. The VMM operation was performed, and the maximum values from the 10 sets were classified as the outputs of the inferencing operations. The digit with the maximum output signal was classified according to the max-current sensing rule³⁶.