Fig. 2: Design and implementation of standard logic gates.
From: An ultra energy-efficient hardware platform for neuromorphic computing enabled by 2D-TMD tunnel-FETs
a Static characteristics of a minimum sized 2D-TFET- and LSTP- inverter, implemented with transistors of the same effective width and channel length, and simulated at VDD = 0.4 V. b Energy-Delay-Product (EDP) comparison of a 2D-TFET- and LSTP- transistor driving an output capacitance varying from 1 aF to 1 fF. The delay \(({t}_{{{{{{\rm{p}}}}}}}={t}_{2}-{t}_{1})\) has been calculated from the time taken by the input signal to reach VDD/2 \(({t}_{1})\) to the time taken for voltage at the output node (OUT) to drop to VDD/2 \(({t}_{2})\). The average energy consumption is calculated by multiplying the average power consumed during \({t}_{1}\) to \({t}_{2}\) with the transition time \(({t}_{{{{{{\rm{p}}}}}}})\). c Schematic of the 11-stage ring oscillator considering interconnect parasitics and minimum-sized inverters. Ring oscillator implemented with minimum sized d LSTP and e 2D-TFET with an oscillation frequency of 10 GHz and 57 MHz, respectively. Enhanced Miller overshoot is observed in e. f All-2D implementation of a 6T-SRAM design, with 2D-FETs being the access transistors and 2D-TFETs being the inverters. Schematic shows the Word Line (WL) and Bit Line (BL) signals. g Simplified schematic of f showing probed node voltages V1 and V2. h Noise margins of the simulated SRAM circuit at VDD = 0.9 V. The static noise margin (hold margin) has been simulated by sweeping V1 and V2, keeping M5 and M6 disconnected, while for read (Q=1) and write (Q=1) margin simulations, \({BL}\) and \(\overline{{BL}}\) have been connected to VDD/VDD and 0/VDD, respectively. Read margin is the lowest at 0.28 V. i All-2D-TFET-SRAM designed completely with 2D-TFETs, which addresses the problem of unidirectionality in TFET current transport. j Simplified sketch of i. k Hold, read (Q=1), and write (Q=0) margin simulations of the all-2D-TFET SRAM simulated with a VDD of 0.7 V assuming the same bias conditions for the Bit Lines as in h. The noise margins are similar as compared to those in h even with a reduced supply voltage of 0.7 V w.r.t 0.9 V in h. l Simulation of node voltages during read operation of the SRAM in i. Plot shows a small increase of the node voltage of \(\bar{Q}\) and a slight decrease of the \(\overline{{BL}}\) voltage, but below the inverter tripping voltage.
