Fig. 3: Dual Conditional (DC) logic scheme based on the CuTeHO device.
From: Tunable stochastic memristors for energy-efficient encryption and computing
a Schematic diagram and two conditions of the DC logic. Logic input ‘0’ is defined as the ground potential, and logic input ‘1’ is defined as one of the two conditions. Similar to the memristive PUFs, the LRS and HRS of the memristor are represented as logic outputs ‘1’ and ‘0’, respectively. b Finite state machine of the CuTeHO device. c I–V curves of the CuTeHO device at Icc = 60 nA. d Experimental demonstration of the finite state machine. Two gray panels in each subfigure are read operations before and after the logic operation. Yellow and blue panels show the transition processes when the initial resistance state is ‘0’ and ‘1’, respectively. e Logic sequences for 16 logic operations.
