Fig. 1: Modelling CMOS spin qubits.
From: Bounds to electron spin qubit variability for scalable CMOS architectures
a Example scaled architecture of a 49 qubit device. b The quantum dots are formed below the computer-generated rough surface. c Model of the three-dot devices measured in this paper. The metallic gates are coloured by their order of deposition in different layers. d–g Comparison between device cross sections in TEM images and computer model. d, TEM image of device T1, showing a cross-section of the device located approximately at the position of the violet rectangular region in (c). e TEM of device T2 with a focus on the silicon oxide interface. We highlight in (d) a square region with the same size. f Cross-section of model at the green rectangular region in (c). g Atomistic simulation showing the electronic wavefunction of a quantum dot below rough Si-SiO2. h Average power spectral density (PSD) of the Si/SiO2 interface comparing the interface from transmission electron microscopy (TEM) images of device T1 (blue) and T2 (d) (cyan), and the computer-generated surface in (a) (see also Supplementary Fig. 1 and Methods). The data were plotted as a function of \(\lambda=\frac{2\pi }{q}\), where q is the wave number. This allows us to compare λ with the most relevant length scales, namely the silicon lattice parameter (aSi = 0.543 nm), the dot diameter (10–15 nm), the double dot length (80–100 nm) and the lateral length of the simulation cell containing all 7 × 7 dots (500 nm). i Average RMS of segments of length λ for the random surface generated numerically and for devices T1 to T6. Error bars indicate the standard error estimated from repeated measurements across multiple TEM images. (see Methods and Supplementary Table 1). Source data of figures e, h, i are provided in the Source Data file.
