Fig. 4: Switching characteristics exhibiting nonvolatile memory of a Te nanowire self-gated ferroelectric field-effect transistor (SF-FET).
a Schematic showing the device structure. b Rds–Vg characteristics for the Te nanowire and nanosheet SF-FETs (upper) and gm–Vg hysteresis loop of Te nanowire SF-FET (lower). c Nonvolatile switching of Rds measured after applying multiple Vp square pulses with the pulse width of 25 s, exhibiting multilevel resistive states. d Schematic showing polarization bound charge distribution with an external electric field applied and band structures for LRS and HRS at zero field. e Rds–Vp hysteresis loops at Vds = 0.5 V. Measurement of each data point is performed at Vg = 0 V after waiting for 1 min following applying each Vp pulse width of 20 ns, 100 ns, 1 μs, and 10 μs. f Nonvolatile resistive states switched by different Vp. Resistive states are measured after applying Vp pulses (from −100 V to 100 V then back to −100 V in steps of 10 V) of 100-ms width. The inset is the linear Ids–Vds characteristics after applying different Vp pulses labeled.
