Fig. 5: Logic gates constructed using GdOCl/MoS2 transistors.
From: Single-crystalline High-κ GdOCl dielectric for two-dimensional field-effect transistors
a Structure schematic of the fabricated logic device. b The truth tables for the logical functions of “NOT”, “OR”, and “AND” realized by different gate inputs. c Voltage transfer characteristics of an NMOS inverter constituted by two GdOCl/MoS2 FETs with the bias voltage (Vdd) ranging from 1 V to 5 V. d The corresponding voltage gains of the resulting inverter in Figure (c). e Transfer curves of top-gate (VINA) transistors at different VINB. f Logic OR gate implemented with varying VINA and VINB values. g Channel current as a function of VINA for varying VINC values. h Logic AND gate implemented with varying VINA and VINC values.
