Fig. 2: Larger contact area defines the most dedoped region of the channel leading to high-gain, densely packed conformable complementary circuits.
A Output characteristics of an asymmetric IGT (gray). Red and black curves demonstrate ID of asymmetrical and symmetrical contact area-based IGTs respectively, in the absence of a gate potential. 1st. B Optical moving-front measurement of the channel of a symmetric (left) and asymmetric (right) gateless PEDOT:PSS-based transistor. Doping-state determined by image subtraction of data generated in the unbiased condition from that acquired after application of –0.6 V bias from source to drain (W, L = 100 µm AD = 100 ×100 µm2, As = 100 ×1500 µm2). Lower plots demonstrate vertical summation of pixel intensity at each horizontal channel/contact position (red dashed lines demarcate transition between contact and channel). Note the upper and lower graphs are aligned, as indicated by red and white dashed lines. C Output characteristics of a cIGT pair based on PEDOT:PEI blend with comparable current range. Inset: optical image of a conformable array of 129032 cIGT pairs placed on the surface of a flapping wing of a live butterfly (scale bar, 10 mm; VG range = –0.1–0.6 V). D Optical micrograph of a densely packed cIGTs (258064 transistors/cm2; scale bar, 100 µm). Inset shows magnified colorized image of 4 pairs of cIGTs (scale bar, 10 µm). E Transient response of 3rd (blue) and 1st (red) quadrant operating transistors, as well as cIGT-based (black) common-source amplifier generated by square pulse input signals (top; VG = 500 mV; 500 kHz, bottom: VIN = 100 µV; 500 kHz). Time constants were obtained from fitting the voltage response to an exponential function (dashed lines). F cIGT voltage gain as a function of frequency demonstrating a uniform 46 dB (~200 V/V) gain with 2 MHz corner frequency (Vin = 100 µVpeak-to-peak). G Comparison of complementary transistors based on the maximum transconductance and time constant for n- and p-type materials. Transistor density was calculated using the highest density of operable devices within a circuit.
