Fig. 1: Schematic illustrations of silicon-IC test structures (dimensions not to scale).
a A wire-bonded IC partially coated with PDMS, covering the wire-bonds and regions of the outer IC surface, leaving most of the IC structure and sidewalls exposed. b A cross-sectional schematic demonstrating the multilayer stack of a representative 6-metal CMOS process, from bottom to top: the source and drain diffusion regions implanted in the Si-substrate, metal layers 1 to 6 (M1 to M6) with M6 being the top-most metal, and where each metal layer is insulated with a SiOX intermetallic dielectric (IMD), and the final passivation layers generally made of SiOX and SiNX. c–e Schematic of implemented test structures in silicon-IC, from simple to more advanced with, c an interdigitated capacitor (IDC) structure implemented using the top metal layers where the structure is closer to the surface, d A planar metal oxide semiconductor (MOS) transistor with the drain, source, and gate implemented in the Si-substrate boundary, making the MOS structures the most buried structure. e A dielectric sensor array with on-chip sensing circuitry for in situ monitoring of insulation and dielectric changes. Dielectric changes between different metal layers (M6-M5, M5-M4, and M4-M3) are sensed using on-chip MOS transistor circuitry.
