Fig. 2: Silicon-IC test structures prepared for long-term accelerated in vitro and in vivo aging.

a–c ICs wire-bonded and prepared for in vitro accelerated aging (voltage and temperature) in phosphate-buffered saline (PBS, pH ~ 7.4) at 67 °C, a Optical image of a Chip-A and B IC placed on ceramic substrates, wire-bonded and partially PDMS-coated, b Tilted optical micrograph of a representative Chip-A sample with the M3-IDC test structure wire-bonded and locally PDMS-coated, leaving most of the chip surface and sidewalls exposed, c Optical image of a partially PDMS-coated Chip-B fully immersed in PBS solution at 67 °C. d, e Top view optical micrographs and cross-sectional SEM images of Chip-A and B ICs with d Optical micrograph of a Chip-A IC fabricated in a 0.35 µm 4-metal CMOS process with two IDC test structures (left). Cross-sectional SEM image of the M3-IDC test structure showing the interdigitated metal structures and the top SiN_X/SiO_X passivation layers (right). e Optical micrograph of Chip-B showing various IDC and MOS transistor test structures fabricated in a 0.18 µm 6-metal CMOS process (left). Cross-sectional SEM image of M5-IDC test structure showing Metal-5 and the top SiN_X/SiO_X passivation layers (right). f ICs subcutaneously implanted in rats. Chip-A and Chip-B ICs are positioned on soft PDMS substrates and locally coated with PDMS, covering the aluminum pads and regions of the top passivation while leaving most of the IC surface exposed to the body. Note that ICs used for the animal study are not wire-bonded.