Fig. 3: Long-term electrical performance of test structures on Chip-B during accelerated aging in PBS solution at 67 °C. | Nature Communications

Fig. 3: Long-term electrical performance of test structures on Chip-B during accelerated aging in PBS solution at 67 °C.

From: On the longevity and inherent hermeticity of silicon-ICs: evaluation of bare-die and PDMS-coated ICs after accelerated aging and implantation studies

Fig. 3: Long-term electrical performance of test structures on Chip-B during accelerated aging in PBS solution at 67 °C.

a Electrochemical impedance spectroscopy (EIS) results of representative M5-IDC test structures without (top, n = 4) and with a top-metal (M6) shield (bottom, n = 4), showing stable capacitive characteristics over the duration of aging. Results are given as average and standard deviation (n = 4). b Top view optical micrograph and average VGS-IDS transfer characteristics of NMOS transistors at 0-month and 12-month (n = 4 unshielded and n = 1 shielded MOS structures). Schematics show the distance between the test structures and the surface of the IC which is exposed to PBS solution (dimensions not to scale). c Top view optical micrograph of the dielectric sensor with a high magnification image of the pixels (left). Measurement results giving the value of each pixel within the array (total 5382 pixels) at 0-month and 5-month (n = 1). Comparing the average and standard deviation of the entire array at 0-month and 5-month show minimal change (right). All electrical measurements are performed while the ICs and their PDMS-coated wire bonds are fully submerged in PBS solution.

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