Fig. 3: ReRAM device and array characterization.
From: Layer ensemble averaging for fault tolerance in memristive neural networks
a Zoomed-in device micrograph of a small subarray within the 20,000-device chip. b Device retention data showcasing effective 2-bit tuning of a representative device. The error bars indicate three standard deviations. States \({G}_{{ON}}\) and \({G}_{{OFF}}\) are utilized for the neural network implementation. c Current vs. voltage (I-V) sweep curves over 20 cycles of a single representative device from the chip showing low cycle-to-cycle variability. d Conductance map and e corresponding conductance distributions of devices in a kernel randomly programmed to one of four conductance states from (b). The color map is clamped at \(300\,{\rm{\mu }}{\rm{S}}\) for clarity; actual stuck-at high conductances are significantly higher, averaging \(500\,{\rm{\mu }}{\rm{S}}\). f Comparison of theoretical accumulated currents and experimental accumulated currents on the kernel for 100 randomly generated input voltage vectors repeated for a total of 20 iterations showing effective multiply-and-accumulate and vector-matrix multiplication operations. All experimental results are gathered using the Daffodil mixed-signal prototyping platform.
