Fig. 1: Step-necking growth of ultrathin and short SiNW channels.
From: Step-necking growth of silicon nanowire channels for high performance field effect transistors
a Illustration of a conventional fin-type field-effect transistor (finFET) architecture for logic circuits, featuring a narrow channel and wider source/drain (S/D) contacts. Fabrication involves extreme ultraviolet lithography (EUV) for patterning and epitaxial growth for the S/D regions. b,c Demonstration of the step-necking catalytic growth technique, which results in a distinctive thick/thin/thick channel profile. As depicted in f SiNWs grown over a convex edge exhibit a narrowed (necked) diameter (Dneck) compared to those on a flat substrate (\({{\rm{D}}}_{{\rm{nw}}}^{{\rm{flat}}}\)) when the curvature radius of the bending track (Rb) is comparable to the size of indium catalyst droplet (Rc). d Schematics of a guided growth of a parallel array of IPSLS SiNWs to grow over a jumping step to form an array of necked SiNWs with middle diameters <20 nm and a short channel length (Lch) of <100 nm. e Short-channel FET built upon necked SiNWs, where the thin middle serves as the channel and two thick ends as de facto source/drain electrodes. g Detailed fabrication steps for the step-necking SiNWs, including guiding step formation, jumping step etching, catalyst deposition/a-Si precursor coating, and annealing growth.
