Fig. 6: Experimental demonstration of the addressable pixelated mode for a 2D array display.
From: Electrically programmable pixelated coherent mid-infrared thermal emission
a Picture (scale bar: \(5\,{{{\rm{cm}}}}\)) of the custom-designed printed circuit board (PCB)-integrated active metasurface system. b Magnified image (scale bar: \(25\,{{\upmu }}{{{\rm{m}}}}\)) of the \(3\times 3\) pixelated 2D metasurface array, accompanied by a schematic depiction of wire bonding. c Sweep mapping of \({{I}}_{d2}\) -\(\,\left({V}_{g1},{V}_{g2}\right)\) under \({V}_{d2}=50\,{{{\rm{mV}}}}\) where the 3rd gate is grounded. For each \({V}_{g1}\) value, sweeping \({I}_{d2}\) -\(\,{V}_{g2}\) maintains the bipolar transport curve of the Gr-FET. Tuning \({V}_{g2}\) enables control over the \({V}_{{{{\rm{Dirac}}}}}\) alignment for pixel on/off. Setting apart from \({V}_{{{{\rm{Dirac}}}}}\) (Point A) boosts the overall current for pixel brightness. Symmetrically, this approach applies to \({I}_{d2}\)- \({V}_{g1}\) sweep under \({V}_{g2}\) control, represented by Point B. d Thermal mapping image (scale bar: \(25\,{{\upmu }}{{{\rm{m}}}}\)) under three gate voltages \(\left[{V}_{g1},{V}_{g2},{V}_{g3}\right]\) in \(\left[-2,\,2,\,-2\right]\,{{{\rm{V}}}}\). The discrete adjustment of gate electrodes under \({V}_{d}=5\,{{{\rm{V}}}}\) results in pixel resistances \(\left[{R}_{1},{R}_{2},{R}_{3}\right]=[529,\,1877,\,1023]\,\Omega\) lighting up the central pixel. e Thermal mapping images (scale bar: \(25\,{{\upmu }}{{{\rm{m}}}}\)) of individual frames displaying the letter “L”.
