Fig. 8: Experimental demonstration of low-crosstalk dual-gate pixelated array.

a Schematic of dual-gate controlled Gr-FET pixels. Pixels are connected in parallel with shared source line (\({V}_{S}\)) and drain line (\({V}_{D}\)). Four L-shaped pull-up (PU) transistors are located at the four corners and the square-shaped heating Gr-FET (heater) is located at the pixel center. b Simplified circuit diagram. c Operating scheme of a dual-gate pixel with PUs having larger intrinsic resistance than the heater. The yellow and blue shaded dash circles with their respective cross marks indicate the local gate value \({V}_{{GS}}\) of the PUs and heater when a pixel is turned on (Fermi level \({E}_{F}\) (dot line) of the PUs decreases to the valence band) or off (\({E}_{F}\) of the heater decreases to the valence band). d Optical microscope image (scale bar: 20 μm) of a one-by-two array. e–h Temperature distributions measured via IR thermal mapping under different on/off \({V}_{{GS}}\) combinations with constant \({V}_{{DS}}=5\,{{{\rm{V}}}}\) (scale bar: 20 μm). Black-line squares represent the pixels in the off state.