Fig. 4: Hardware convolutions using GIM 2D FGMs array.

a Photo (left, scale bar: 1 mm) and OM image (right, scale bar: 40 μm) of the wired 9 × 2 array. The electrode lines are also shown. The channel’s width/length is 3.95/2.47 μm (see Supplementary Fig. 33 for detailed geometric parameters). b Parallel programming method for a selected row of the array. c Illustration of the vector-matrix multiplication operation for image convolution. The kernel weights were mapped as conductance states of the device array before each convolution process. During the convolution process, 3 × 3 patches of pixels were converted to drain voltage inputs patch-by-patch, with the patches sliding through the whole image row-by-row. d Conductance maps of three kinds of kernels that were mapped to the array. e The corresponding convolution results mapped into the source-drain current. f Comparisons between output current distributions in (e) (hardware) and software-based convolution results. The results have been normalized. g Illustration of the VGG16 convolutional base structure. There are 5 convolution blocks with each containing several convolution layers and a pooling layer. h, i Hardware-based conductance maps of the two convolution layers in block 1 (h) and the corresponding software-based weight maps (i). j, k The corresponding histogram plots of hardware-based conductances (j) and software-based weights (k).