Fig. 3: One-step simultaneous transfer and integration of contact electrodes and the entire gate stack. | Nature Communications

Fig. 3: One-step simultaneous transfer and integration of contact electrodes and the entire gate stack.

From: Sacrifice-layer-free transfer of wafer-scale atomic-layer-deposited dielectrics and full-device stacks for two-dimensional electronics

Fig. 3: One-step simultaneous transfer and integration of contact electrodes and the entire gate stack.

a Schematic diagram of one-step transfer process to fabricate fully encapsulated top-gated transistors, which involves pre-fabricating the entire top-gated device stack on mica and laminating it onto the surface of target channel materials. b Typical OM image of pre-fabricated entire device stack on mica, including top-gated two-terminal field-effect transistors (FETs) and six-terminal Hall-bar device. c Corresponding OM image of the entire top-gated device stack after delaminating and picking up from mica substrate. Here, the PMDS acts as the rigid support substrate to reduce the wrinkles during the transfer process. d Enlarged OM image in the white dotted box area in (c). e Typical AFM image of as-transferred gate stack (Al2O3/Pd/Au) on PDMS substrate, showing an atomically flat surface (Ra ~0.15 nm) when peeled off from the mica substrate. f Typical OM image of a top-gated MoS2 FET fabricated on SiO2/Si substrate by one-step vdW transfer. The underlying MoS2 sheet was marked out by the dash line. g Corresponding cross-sectional bright-field scanning transmission electron microscope (STEM) image of as-transferred MoS2 FET, showing a perfect interface and as-expected stacking sequence of Al2O3/MoS2/SiO2.

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