Fig. 4: As-transferred fully gated MoS2 transistors with improved on-state current and ignorable gate hysteresis.
a Cartoons of two different device configurations adopted in top-gate FETs, whose top-gate stack partially encapsulate or fully encapsulate the underlying MoS2 channel (namely partially gated or fully gated FETs). b Typical dual-sweep transfer curves of the as-transferred MoS2 transistors with a fully gated and a partially gated device configuration. Apparently, the fully gated FET exhibited a much larger on-state current and switching ratio than the partially gated one. The thickness of MoS2 was kept the same as ~1.5 nm. The insets are the OM images of fabricated fully (left) and partially (right) gated FETs (scale bar, 20 μm). c The corresponding output curves of the devices in (b), in which the gate voltages Vg varied from 1.5 V to −1.7 V with a step of −0.25 V. The on-state current of fully gated FET is higher (> 42 times) than that of partially gated FET with the source-drain voltage Vds = 1 V. d The transfer curves of the fully gated MoS2 FET under different Vg sweep ranges. e Corresponding transfer curves with different gate-voltage sweeping speeds ranging from 0.05 to 0.25 V s−1. f, g Extracted bias-range (f) and sweep-rate (g) dependent gate hysteresis from the dual-sweep transfer curves in (d) and (e).
