Fig. 6: Technical challenges and opportunities for future development of EGC and QGC.

a Current and future directions for EGC. The leftmost panel illustrates the current state of EGC, showing various types of self-rectifying memristors (upper panel) integrated with CBA structures designed for planar graphs (lower panel). Progressing to the right, the figure highlights research directions to improve hardware efficiency and expand the scope of solvable problems in EGC. Developing rectifying devices with Ohmic characteristics under forward bias is required to decrease latency, along with advancements in CBA structures to support multidimensional and hierarchical graphs (middle panel). Furthermore, achieving reconfigurability in EGC hardware requires exploring devices and CBA structures capable of physically representing SGM current paths. Obtaining precise SGM current path information plays a critical role in mitigating EGC’s limitation of sequential operation. b Current and future directions for QGC. The leftmost panel depicts the current QGC, utilizing a two-level system and a low-dimensional graph. Progressing to the right, the future vision for QGC involves adopting high-dimensional, multifunctional devices to enable multi-level systems with high-order interaction edges. c Suggested clustering for EGC and QGC. A raw graph is first clustered into smaller graphs, which can be processed in a single core. After either time- or spatial multiplexing, the processed results from clustered graphs are integrated for the final output.