Fig. 1: Overview of MoS₂-Memtransistor-based Crossbar Array Architecture.

a Schematic of the basic non-volatile memory (NVM) cell design containing a single memtransistor. Terminals are split into row (drain and gate) and column (source) accesses, with each cell occupying an area of 676 µm². b Optical image of a representative 16 × 10 crossbar array based on the design shown in (a). Zoomed-in image shows constituent memtransistors with the drain, source, and gate lines labeled. Scale bar denotes 100 µm (10 µm for zoomed-in). c Overlapped transfer characteristics, i.e., drain-to-source current (I_DS) versus back-gate voltage (V_BG), taken at a drain-to-source voltage (V_DS) of 1 V from constituent memtransistors. d Hysteresis loops for a representative device from (b, c) taken at V_DS = 1 V. Multiple loops were taken by sweeping V_BG over the noted ranges to determine the presence/size of the memory window at different gate voltages; a sizable memory window of ~ 7 V can be noted for the +/− 10 V sweep. e Three-dimensional scatter plot showing the distribution of ON-state and OFF-state currents taken at V_DS = 1 V, denoted as I_ON (pink) and I_OFF (cyan), respectively; devices/cells marked in gray registered as an open circuit (OC) when measured. Notably, 158/160 devices were found to work (98.8% yield). f, g Maps of (f) threshold voltage (V_th) and (g) subthreshold slope (SS) across the array. OC devices are marked. h, i Histograms of (h) V_th and (i) SS. The means (µ) and standard deviations (σ) are noted for each.