Fig. 3: Demonstration of MNIST Handwritten Digit Classification on a 2 kb Memtransistor Crossbar Array.

Optical images of (a) a 1.5 × 1.5 cm chip containing a 64 × 32 crossbar array comprising 2048 MoS₂ memtransistors, including (b) a zoomed-in image showing the full 2 kb array (scale bar of 100 µm) and (c) a further zoomed-in image showing nine constituent memtransistors (scale bar of 10 µm). d Schematic showing preprocessing performed on training and test (inference) images taken from the Modified National Institute of Standards and Technology (MNIST) database. The original images (28 × 28 pixels) were downscaled to 13 × 13 pixels and binarized to fit into a 64 × 30 sub-array for this demonstration. Downscaled images were then converted to 169 × 1 input vectors and split into three sub-vectors for input to the array. A dataset comprising 10,000 resized/reshaped images were then used for training and weight assignment; for this demonstration, simulated weights were split between logic “0” and “1” and later converted to targeted conductance states for hardware implementation. e Heatmap showing the distribution of simulated weights following training. A test dataset of 1000 resized/reshaped MNIST images was fed to the simulated array for verification of network inference/classification. f Confusion matrix showing the classification results for the simulated inference check described in (e). An overall accuracy of 88.1% was achieved. g Heatmap showing the distribution of conductance states assigned to the hardware array in respect to the simulated weight distribution shown in (e), with weights of “1” mapped to a conductance state of ~ 50 nS and weights of “0” mapped to the OFF-state conductance (a few pS). Cells marked NaN either display an open circuit or high gate leakage; the overall yield of devices remained high at ~ 92.2%. h Hysteresis characteristics of the 1770 working devices in the 64 × 30 sub-array extracted at V_DS = 1 V, which show low intrinsic device-to-device variation, memory windows > 5 V, and read margins > 10⁴. i Histogram showing the distribution of the final conductance states (weights) represented in (g). j Confusion matrix showing the classification results for hardware-based inference performed on the memtransistor array shown in (a–c) as per the conductance state (weight) distribution shown in (g). A test dataset comprising 1000 resized/reshaped MNIST images was applied to the drain terminals of the array as voltage inputs (either 0 V or 1 V, depending on the corresponding pixel value); output currents along corresponding columns/nodes were then individually registered and compared to all other outputs to determine the inferred digit for each case. An overall accuracy of 85.6% was registered.