Fig. 2: Bit abstraction of the origami switching element and the construction and testing of a reconfigurable logic gate.

a 0-input and 1-input of the origami unit-cell as a logic element. b The Buffer origami switching elements and logic function demonstrations. c The NOT origami switching elements along with their input and output demonstrations. d Construction and reconfigurable schematic of AND, OR, NOR, and NAND logic gates based on integrated circuit switch theory. An inverted input (‾) corresponds to a NOT switching element, and an ordinary input corresponds to a Buffer switching element. e The physical images of four mechanical inputs and displacement-force curves of the origami unit-cell in series under compression. f The physical images of four mechanical inputs and displacement-force curves of the origami unit-cell in parallel. g Designed AND, OR, NOR, and NAND reconfigurable logic gates using Buffer and NOT origami switching elements. Conductive networks 1, 3, and 4 are used for logical operations, while conductive networks 2 and 5 are used for indicating the folding states of the unit-cells. i.e., the inputs. h The physical demonstration of four possible input and output results for the designed AND-OR logic gate with the AND logic function. The blue or red light indicates that one of the two inputs is 1, while no light indicates an input of 0. The green light indicates that the logic gate output is 1, and no light indicates an output of 0. i The physical demonstration of four possible input and output results for the designed AND-OR logic gate with OR logic function.