Fig. 3: Construction and multitask functionality of a reprogrammable gate meta-array based on reconfigurable AND-OR and NOT-Wire logic gates.

a Cascading network diagram of the reprogrammable gate meta-array as a 2-bit adder, along with a demonstration of the example of 3 + 2 = 5 and the graph of output electrical signal results for 16 possible inputs. The reprogrammable gate meta-array is constructed by four inputs (a, b, c, d), four outputs (e, f, g, h), 8 NOT-Wire gates (1–8), and 22 AND-OR gates (14–30). Vcc represents high potential input. Orange-red, yellow, green, and purple regions represent abcd-e, abcd-f, abcd-g, and ac-h cascading networks, respectively. Simplified Boolean expressions and cascading network relationships are shown at the bottom. Solid lines represent AND, dashed lines represent OR, and overlines represent NOT operations. Roman numerals I-IV denote logical network levels. The formulas for the 2-bit adder and corresponding input-output relations for 3 + 2 in binary and decimal are also shown. Connected paths that result in an output of 1 are highlighted in Cyan. Green-numbered results show the inputs of NOT-Wire and AND-OR logic gate. b Cascading network diagram of the reprogrammable gate meta-array as a 2-bit subtractor, along with a demonstration of the example of 3 − 2 = 1 and the graph of output electrical signal results. c Cascading network diagram of the reprogrammable gate meta-array as a 2-bit comparator, along with a demonstration of the example of 3 > 2 and the graph of output electrical signal results. d Cascading network diagram of the reprogrammable gate meta-array as a 2-bit comparator, along with a demonstration of the example of 3 × 2 = 6 and the graph of output electrical signal results.