Fig. 8: Standardized hysteresis measurements performed on gate-all-around Bi₂O₂Se/Bi₂SeO₅/Au MOSFETs.

a Geometry of the gate-all-around Bi₂O₂Se/Bi₂SeO₅/Au MOSFETs studied in this work⁶². b Transmission electron microscopy (TEM) image of the Bi₂O₂Se/Bi₂SeO₅/Au gate stack, used to determine the oxide thickness as a function of oxidation time. c Determination of the standardized sweep range based on an I_d–V_g curve measured prior to the hysteresis measurements. The subthreshold region is fitted with a straight line (black solid), yielding a subthreshold slope of S = 122 mV/dec. The effective threshold voltage V_th and current I_th, used to define the sweep range according to Eq. (7), are obtained as the point where the drain current deviates by more than 5 % from the ideal subthreshold behavior. d Bare hysteresis curves for devices with different Bi₂SeO₅ thicknesses. e Maximum hysteresis width as a function of Bi₂SeO₅ thickness, showing a linear increase with thickness. f Normalized hysteresis curves for devices with different Bi₂SeO₅ thicknesses. The collapse of all curves onto a single characteristic profile confirms that, when adopting the standardized measurement scheme, the hysteresis becomes approximately independent of insulator thickness.