Fig. 2: Performance characterization of the floating gate synaptic transistor.
a Schematic illustration of the floating gate synaptic transistor structure. b Transfer characteristic of the device, with a memory window reaching 11.2 V at Vds = 1 V when Vgs is swept from −10 V to 10 V. The inset shows the transfer curve for Vgs swept from −5 V to 5 V. c Conductance modulation through 16 negative/positive Vgs pulses with the operating mechanism of this synaptic transistor. d Absolute change in conductance (ΔG) as a function of Vgs pulse amplitude (top; pulse width = 1 ms) and pulse width (bottom, Vgs = −7.5 V). e Switching of conductance state under −15 V Vgs pulse of 100 µs. f Conductance changes induced by 100 consecutive negative and positive Vgs pulses at 7.5 V amplitude and 100 μs width. The inset depicts multiple conductance states. g Endurance performance of the synaptic transistor executed with alternate positive and negative Vgs pulses ( ± 15 V, 1 ms). h Retention stability of the synaptic transistor after 10 negative/positive Vgs pulse, demonstrating stable high- and low-conductance states. i Comparison with previously reported studies, where the range of the blue ellipse is derived from the mean and standard deviation of the data points in the most advanced research progress in recent years. The centroid represents the mean of the data, while the boundary of the ellipse corresponds to the 95% confidence interval. Further details can be found in Supplementary Table 1. j, k Optical images of the floating gate synaptic transistor array (j; scale bar, 100 µm) and its bonded chip (k; scale bar, 1 mm). l Variations in pulse modulation among devices in the 4 × 4 array. Each device is modulated by 16 consecutive negative/positive Vgs pulses with the duration of 1 ms and amplitude of 7.5 V. The blue solid line and blue envelope represent the mean and variance of conductance of 16 devices under Vgs pulses.
