Fig. 1: Hardware topology of the proposed architecture. | npj Quantum Information

Fig. 1: Hardware topology of the proposed architecture.

From: Compilation and scaling strategies for a silicon quantum processor with sparse two-dimensional connectivity

Fig. 1

a Linear segment of m = 4 qubits (dots) connected by two-qubit operations (lines), representing split-gate transistors along a nanowire. b Hardware junction joining four linear qubit segments. Orange lines indicate two-qubit operations combined with spin shuttling. c Unit cell of the proposed architecture with m = 4 qubits in each segment. d Hardware graph of the proposed architecture with dx = 2 and dy = 3 unit cells in x and y directions, respectively.

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