Fig. 5: Compilation overhead of Case I.
This is expressed via a average and b maximum shortest path as a function of the number of qubits for different layouts—a (1D) linear layout, a (2D) rectangular device with nearest neighbor connectivity with lx = ly and the proposed architecture in a square arrangement dx = dy with m = 4, 8, and 16. Lines indicate the scaling and dots indicate qubit numbers which can be realized by an actual device.
