Fig. 5: Parity-check measurement circuits built from conventional two-qubit gates and constructed in ways that the Z-noise bias on the data qubits is preserved under mid-gate errors.

Shown are (a) ZZ, (b) XX, and (c) Z₁X₂ check circuits. The circuits in (a) and (c) preserve the Z noise bias on data qubits even in the presence of mid-gate errors. The circuit in (b) includes a classically controlled X gate targeting one of the data qubits, which is non-Z bias preserving. Data qubits are labelled by Data₁ and Data₂, while the middle qubit in each circuit is a measurement ancilla. In (c), the first equality can be checked by noting that the depth-3 circuit before and after the mid-circuit measurement performs a next-nearest-neighbour CZ gate, if the measurement ancilla is initially in the \(\left\vert +\right\rangle\) state. The second equality can be checked by commuting all gates past the measurement. The grey measurements can be optionally included to provide flag information.