Fig. 2: Logical state preparation circuits and characterization.
a, b Circuits for fault-tolerant (FT) preparation of \(\left\vert 0/{1}_{L}\right\rangle\) and \(\left\vert {\pm }_{L}\right\rangle\) states. The \(\left\vert {1}_{L}\right\rangle\) (or \(\left\vert {-}_{L}\right\rangle\)) state are obtained by applying XL (or ZL) gate after preparing the \(\left\vert {0}_{L}\right\rangle\) (or \(\left\vert {+}_{L}\right\rangle\)) state. c Circuits for non-fault-tolerant (nFT) preparation of arbitrary logical state \(\left\vert {\psi }_{L}\right\rangle\). d–f Density matrices and fidelities of the six single logical states prepared in the experiment. All logical state density matrices are obtained through logical state tomography. g Comparison of fidelity and post-selection (PS) rates between experiments and simulations. The figure shows the fidelity of six logical states and the post-selection rates when measuring their eigenoperators (ZL or XL).
