Introduction

Quantum computing holds the promise to accelerate classical computing in various applications such as large number factorization1, quantum simulation2, and machine learning3. However, physical qubits are typically very fragile and are easily disturbed by environmental noise. To address the noise issues in large-scale quantum computing, quantum error correction techniques have been proposed, which introduce redundant information and encode quantum states onto logical qubits to ensure fault tolerance4,5,6.

In recent years, multiple experiments across various quantum computing platforms have demonstrated the memory of quantum information on logical qubits. These experiments are based on hardware systems encompassing superconducting7,8,9,10,11,12,13,14,15, ion trap16,17, neutral atom18, and other systems19,20,21,22,23. Particularly in experiments using bosonic codes, it has been demonstrated that the quality of logical qubits can exceed the so-called break-even point21,22, validating the effectiveness of quantum error correction techniques in suppressing quantum noise.

Furthermore, to achieve fault-tolerant quantum computing (FTQC), a set of logical gates needs to be implemented. The simplest approach to implement logical gates is transversally, where all physical qubits have interacted with at most one physical qubit from each logical block, therefore naturally ensuring fault-tolerance. However, a well-known theorem states that no quantum code can simultaneously promise a transversal and universal logical gate set24,25,26. For instance, in the surface code, the CNOT gate is transversal. While some single-qubit rotation gates, such as the S gate and T gate, typically need to be implemented indirectly using gate teleportation circuits with ancilla logical states27,28.

Currently, more and more experimental works are focusing on demonstrations of logical gates of various quantum error correction codes12,14,18,29,30,31,32,33,34,35,36,37. For instance, in neutral atom systems, demonstrations of the CNOT, CZ, and CCZ gates have been achieved on the [8,3,2] color code18. In ion trap systems, the H, S, T, and CNOT gates have been demonstrated on the Steane code30, forming a universal gate set. In superconducting systems, experimental demonstrations of logical gates remain limited, particularly for the surface code, which is the most promising encoding scheme due to its high theoretical threshold and practical nearest-neighbor connectivity requirements28,38. Ref. 31 demonstrated a universal set of single-qubit gates on the distance-2 surface code in superconducting systems, showing the potential of using surface code logical qubits for FTQC in the superconducting quantum processor. The main limitation of their work is the lack of two-qubit logical operations, thus not constituting a complete universal gate set. Additionally, the ancilla quantum states used in gate teleportation are physical states rather than logical states, which is inconsistent with the requirements in FTQC. To the best of our knowledge, no work has yet implemented a complete universal set of logical gates in either the superconducting system or the surface code encoding.

In our work, we use the error-detecting surface code with distance 2 (Fig. 1a) to implement a complete set of universal logical gates, including arbitrary single-qubit rotations around the Z or X axis and the CNOT gate, filling the gap in current literature. In the experiment, we encode two logical qubits in a 2 × 4 qubit region of the superconducting quantum processor Wukong (see Fig. 1b and Supplementary Note 1). The logical CNOT gate is implemented transversally, i.e., by performing four CNOT gates between the corresponding physical qubits. Additionally, single-qubit rotation gates are implemented by preparing the ancilla logical states and applying gate teleportation circuit, which consists of a logical CNOT gate and logical X or Z measurement on the ancilla qubit. To implement transversal CNOT gates on a two-dimensional topology, our design has to simplify the encoding of two logical qubits by removing the measurement qubits required for stabilizer measurements. The error detection in our experiment is achieved through measurement and post-selection at the end of the circuit. While no stabilizer measurements are performed after logical operations, any single error can still be detected in fault-tolerant circuits by reconstructing the stabilizers from the terminal measurement results.

Fig. 1: Distance-2 surface code and qubit layout in the experiment.
figure 1

a Two logical qubits of the distance-2 surface code and transversal CNOT gate. Each logical qubit is encoded by four data qubits and the logical CNOT gate between two logical qubits corresponds to the four physical CNOT gates between the corresponding data qubits. b The experiment uses eight physical qubits arranged in a 2 × 4 rectangular region on the superconducting quantum processor Wukong. The deep blue lines represent the topology of the processor, indicating the allowed two-qubit gates between physical qubits.

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The logical Pauli transfer matrices (LPTMs) of these logical gates are characterized on a complete set of states, according to which the gate fidelities are evaluated and listed in Table 1. Using fault-tolerant logical state encoding circuits and transversal CNOT gates, four logical Bell states are also prepared. By verifying the violation of the CHSH inequality with these Bell states, we have confirmed the presence of quantum entanglement between two logical qubits. In the experiment, all fault-tolerantly prepared logical states, including single-qubit states and Bell states, exhibit higher fidelity than the results on the corresponding physical qubits (see Table 2).

Table 1 Summary of the fidelities of logical gates (including characterization) in the experiment
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Table 2 Comparison of the fidelities between fault-tolerant prepared logical states and physical states (including preparation and characterization) in the experiment
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Note that the fidelity referred to here is the overall fidelity of the preparation and characterization process, therefore, it does not indicate that a logical state beyond the break-even point has been achieved. However, as hardware improves, the logical error rate of error detection codes could exceed the breakeven point, as indicated by some theoretical and experimental work using error detection codes in the context of early fault-tolerant computing39,40.

Moreover, in the long term, the demonstration of transversal CNOT gates on surface codes could support more efficient FTQC. Theoretical works suggest that combining transversal CNOT gates with two-dimensional (2-D) operations has the potential to reduce the space-time overhead of FTQC on surface codes41,42. However, we recognize that this may be a rather distant goal for superconducting systems, as the transversal CNOT gate for surface codes typically requires a multi-layer architecture or a 2-D architecture with long-distance couplings43,44,45,46. Nonetheless, our experiment provides an early exploration for these intriguing applications.

Results

Logical state preparation and measurement

The logical qubit of distance-2 surface code is encoded on four data qubits and is capable of detecting any single-qubit errors. Its code space is the +1 eigenspace of the following stabilizer group:

$${\mathcal{S}}=\langle {X}_{1}{X}_{2}{X}_{3}{X}_{4},{Z}_{1}{Z}_{2},{Z}_{3}{Z}_{4}\rangle .$$
(1)

Then the logical Pauli operators are defined as:

$${Z}_{L}={Z}_{1}{Z}_{3},\quad {X}_{L}={X}_{3}{X}_{4}.$$
(2)

Accordingly, the explicit form of the logical state can be written as:

$$\begin{array}{rcl}\left\vert {0}_{L}\right\rangle &=&\frac{1}{\sqrt{2}}(\left\vert 0000\right\rangle +\left\vert 1111\right\rangle ),\\ \left\vert {1}_{L}\right\rangle &=&\frac{1}{\sqrt{2}}(\left\vert 0011\right\rangle +\left\vert 1100\right\rangle ),\end{array}$$
(3)

and

$$\left\vert {\pm }_{L}\right\rangle =\frac{1}{\sqrt{2}}(\left\vert {0}_{L}\right\rangle \pm \left\vert {1}_{L}\right\rangle ).$$
(4)

Here, we designed circuits for preparing the logical states \(\left\vert {0}_{L}\right\rangle\), \(\left\vert {1}_{L}\right\rangle\), \(\left\vert {+}_{L}\right\rangle\) and \(\left\vert {-}_{L}\right\rangle\) fault-tolerantly (see Fig. 1), whose fault tolerance is proven in the Methods. In this error-detection context, an operation is fault-tolerant if any single error produces a non-trivial syndrome and can therefore be post-selected out. In order to simultaneously ensure fault-tolerant state preparation and transversal CNOT gate implementation between \(\left\vert {\pm }_{L}\right\rangle\) and \(\left\vert 0/{1}_{L}\right\rangle\) states, we adopt the qubit allocation scheme depicted in Fig. 2a and b. The key is that we exploit the property that \(\left\vert {\pm }_{L}\right\rangle\) can be decomposed into product states (\(\left\vert {\pm }_{L}\right\rangle =\frac{1}{2}{(\left\vert 00\right\rangle \pm \left\vert 11\right\rangle )}^{\otimes 2}\)), and encode \(\left\vert {\pm }_{L}\right\rangle\) on the leftmost two (q1 and q5) and the rightmost two physical qubits (q4 and q8) in the hardware. Moreover, we also provide a circuit for preparing arbitrary logical state \(\left\vert {\psi }_{L}\right\rangle\) in Fig. 2c. Generally, such a circuit for encoding arbitrary logical state is not fault-tolerant, nor is this circuit. In this way, a logical state can be encoded on a chain of four physical qubits (q1-q4) with only nearest-neighbor coupling.

Fig. 2: Logical state preparation circuits and characterization.
figure 2

a, b Circuits for fault-tolerant (FT) preparation of \(\left\vert 0/{1}_{L}\right\rangle\) and \(\left\vert {\pm }_{L}\right\rangle\) states. The \(\left\vert {1}_{L}\right\rangle\) (or \(\left\vert {-}_{L}\right\rangle\)) state are obtained by applying XL (or ZL) gate after preparing the \(\left\vert {0}_{L}\right\rangle\) (or \(\left\vert {+}_{L}\right\rangle\)) state. c Circuits for non-fault-tolerant (nFT) preparation of arbitrary logical state \(\left\vert {\psi }_{L}\right\rangle\). d–f Density matrices and fidelities of the six single logical states prepared in the experiment. All logical state density matrices are obtained through logical state tomography. g Comparison of fidelity and post-selection (PS) rates between experiments and simulations. The figure shows the fidelity of six logical states and the post-selection rates when measuring their eigenoperators (ZL or XL).

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After preparing the logical states, logical X, Y, or Z measurements are performed to characterize these states. Their measurement results are determined by the product of the corresponding Pauli operator measurement result on each data qubits. The logical X and Z measurements are fault-tolerant and correspond to measurements in the X and Z bases on all data qubits, respectively. Post-selection is carried out based on the conditions provided by the three generators of the stabilizer group, discarding results that violate these conditions. Specifically, assuming the X or Z measurement result on the ith data qubit is \({m}_{i}^{x}\) or \({m}_{i}^{z}\in \{+1,-1\}\) the post-selection conditions are \({m}_{1}^{x}{m}_{2}^{x}{m}_{3}^{x}{m}_{4}^{x}=+1\), and \({m}_{1}^{z}{m}_{2}^{z}=+1\), \({m}_{3}^{z}{m}_{4}^{z}=+1\) for logical X and Z measurements, respectively. On the other hand, measurement of the logical Y operator YL = Z1Y3X4 is not fault-tolerant. It requires Z measurements on data qubits D1 and D2, a Y measurement on D3, and an X measurement on D4. The corresponding post-selection condition is \({m}_{1}^{z}{m}_{2}^{z}=+1\). In this case, post-selection cannot eliminate all single-qubit error cases but can suppress some of them. Define the probability of successfully passing the post-selection condition as the post-selection rate. Since the post-selection conditions vary under different measurement bases, the post-selection rate is significantly influenced by the measurement basis.

Here, we conduct experimental demonstrations and characterizations on the fault-tolerantly prepared \(\left\vert 0/{1}_{L}\right\rangle\), \(\left\vert {\pm }_{L}\right\rangle\) states, and non-fault-tolerantly prepared \(\left\vert 0/{1}_{L}\right\rangle\) states. Through logical quantum state tomography, we constructed the density matrix ρL in the code space, as shown in Fig. 2d–f. Furthermore, we computed the fidelity of the logical state:

$${F}_{L}=\langle {\psi }_{L}| {\rho }_{L}| {\psi }_{L}\rangle ,$$
(5)

where \(\left\vert {\psi }_{L}\right\rangle\) is the ideal logical quantum state. The fidelities of the fault-tolerantly prepared states \(\left\vert {0}_{L}\right\rangle ,\left\vert {1}_{L}\right\rangle\) and \(\left\vert {+}_{L}\right\rangle ,\left\vert {-}_{L}\right\rangle\), as well as the non-fault-tolerantly prepared states \(\left\vert {0}_{L}\right\rangle\) and \(\left\vert {1}_{L}\right\rangle\), are 97.9(2)%, 98.0(2)%, 97.7(2)%, 97.8(2)%, 89.2(3)%, and 88.9(3)%, respectively. We also computed the fidelities of the \(\left\vert 0\right\rangle ,\left\vert 1\right\rangle\) and \(\left\vert +\right\rangle ,\left\vert -\right\rangle\) states prepared on the eight physical qubits in the experiment using physical state tomography. For a fair comparison, we did not use readout error mitigation techniques47 during the physical state tomography. The highest values among eight physical qubits are 96.9(3)% for \(\left\vert 0\right\rangle\) in q2, 94.8(4)% for \(\left\vert +\right\rangle\) in q2, 93.6(5)% for \(\left\vert -\right\rangle\) in q2 and 90.8(6)% for \(\left\vert 1\right\rangle\) in q3. All these values are lower than the fidelities of the fault-tolerantly prepared logical states, demonstrating the noise-suppressing effect in the overall process of the preparation and characterization. However, we remind readers that the fidelities of logical or physical states also affected by noise in the tomography protocol. Due to the difficulty in distinguishing noise in characterization from noise in state preparation, these results do not imply that the fidelity of logical state preparation exceeds that of the physical state. Especially given the significant readout noise on our superconducting processor, the contribution of error detection to the improvement in readout fidelity is likely more substantial.

In addition, we provide information on the post-selection rates when measuring the logical state eigenoperators in Fig. 2e (see Supplementary Note 3 for complete data on the post-selection rate). We also present simulation results for comparison, which are based on the Pauli depolarizing noise model, a commonly used error model in quantum error correction research (see details in Supplementary Note 4). However, we also remark that this model does not fully capture the real noise, leading to discrepancies between experimental and simulated data.

Logical CNOT gate and Bell states

Next, our experiment demonstrates a transversal CNOT gate between two surface code logical qubits (see Fig. 3a and b). Initially, two logical states \(\left\vert {\psi }_{L}\right\rangle\) and \(\left\vert {\varphi }_{L}\right\rangle\), are prepared on two chains of the quantum processor (q1-q4 and q5-q8), where \(\left\vert {\psi }_{L}\right\rangle\) and \(\left\vert {\varphi }_{L}\right\rangle\) are from a complete state set \(\{\left\vert {+}_{L}\right\rangle ,\left\vert {-}_{L}\right\rangle ,\left\vert {0}_{L}\right\rangle ,\left\vert {i}_{L}\right\rangle \}\). Here \(\left\vert {i}_{L}\right\rangle =(\left\vert {0}_{L}\right\rangle +i\left\vert {1}_{L}\right\rangle )/\sqrt{2}\) is the +1 eigenstate of the logical operator YL. This step is realized by the preparation circuit for arbitrary logical states described in the previous section. Since the fidelity of states \(\left\vert {+}_{L}\right\rangle\) and \(\left\vert {-}_{L}\right\rangle\) in our experiment is higher, we prioritize selecting these two states to form the complete state set. The density matrices of the initial logical states are characterized by logical state tomography. Subsequently, a transversal CNOT gate is applied to the initial logical states, and the output states are characterized using logical state tomography. Based on the expectation values of two-qubit Pauli operators of the initial and output states, we extract the LPTMs using the method presented in ref. 31. The fidelity of the logical CNOT gate, as computed from the LPTM, is found to be \({F}_{L}^{G}=88.9(5) \%\). Details concerning the LPTM and fidelity calculation are presented in Supplementary Note 2. Due to the noise in the characterization, this result is actually a conservative estimate of the logical gate fidelity.

Fig. 3: Logical CNOT gate and Bell state characterization.
figure 3

a Circuit of the logical CNOT gate implemented transversally. b, c Circuit for applying a logical CNOT gate on arbitrary logical states \(\left\vert {\psi }_{L}\right\rangle\) and \(\left\vert {\varphi }_{L}\right\rangle\), and the circuit for fault-tolerant preparation of Bell states, respectively. The blocks represent logical state preparation circuits and the logical CNOT gate. The upper half of the logical CNOT block corresponds to the control logical qubit, while the lower half corresponds to the target logical qubit. d Density matrices and fidelities of the four logical Bell states prepared fault-tolerantly in the experiment. e Average fidelity and post-selection (PS) rates of four logical Bell states when measuring XL ⊗ XL, YL ⊗ YL and ZL ⊗ ZL in experiments and simulations.

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Then we use the logical CNOT gate to prepare four Bell states on logical qubits, which are important entangled resources in quantum information. Following the above initialization method, the control and target logical qubits can be initialized to \(\left\vert {\pm }_{L}\right\rangle\) and \(\left\vert 0/{1}_{L}\right\rangle\) states, respectively. Then they can be acted by a logical CNOT gate to generate a Bell state. However, under such qubit allocation, the prepared \(\left\vert 0/{1}_{L}\right\rangle\) state is not fault-tolerant. Therefore, we adopt the qubit allocation scheme from the previous section to simultaneously fault-tolerantly prepare the \(\left\vert 0/{1}_{L}\right\rangle\) and \(\left\vert {\pm }_{L}\right\rangle\) states (see Fig. 3c). This circuit can be viewed as a special planarization of a two-layer architecture. In this layout, all physical CZ gates required in both the logical state preparation and the transversal CNOT gate implementation are 2-D hardware-neighbor. We reconstruct the density matrix of the logical Bell states in Fig. 3d. The overall fidelities in the preparation and characterization for the four logical Bell states are 79.5(5)%, 79.5(5)%, 79.4(5)%, and 79.4(5)%, respectively. We also report the post-selection rates for Bell states under X ⊗ X, X ⊗ X, Z ⊗ Z measurements along with a comparison between simulated and experimental data in Fig. 3e. Correspondingly, we prepare four physical Bell states by physical CNOT gate on qubits q6 and q7. The fidelity of the CNOT gate between q6 and q7 is the highest among all physical CNOT gates in the experiment. The fidelities for the four physical Bell states are 74.4(9)%, 74.2(9)%, 74.5(9)%, and 74.2(9)%, respectively, all of which are lower than the fidelity of the fault-tolerantly prepared logical Bell states.

To confirm entanglement between the two surface code logical qubits, we verify a variant of the CHSH inequality48. For a two-qubit density matrix ρ, define the matrix Tρ with elements \({({T}_{\rho })}_{ij}={\rm{Tr}}(\rho {P}_{i}\otimes {P}_{j})\), where Pi ∈ {X, Y, Z}. A necessary and sufficient condition for violating the CHSH inequality is u1 + u2 > 1, where u1 and u2 are the two largest eigenvalues of the matrix \({T}_{\rho }^{T}{T}_{\rho }\). In our experiment, the values of u1 + u2 for the four logical Bell states are 1.55, 1.55, 1.54, and 1.54, respectively. This result confirms the presence of quantum entanglement between the two surface code logical qubits.

Logical single-qubit rotation

Finally, we demonstrated logical single-qubit rotations around the Z or X axis based on gate teleportation circuit (Fig. 4a). More specifically, these rotation operations are

$${R}_{Z}(\theta )={e}^{-i\theta {Z}_{L}/2},\quad {R}_{X}(\theta )={e}^{-i\theta {X}_{L}/2},$$
(6)

where θ is the rotation angle. The gate teleportation circuit consists of three parts. First, preparing the ancilla states

$$\begin{array}{rcl}\left\vert {\theta }_{L}^{z}\right\rangle &=&\frac{1}{\sqrt{2}}(\left\vert {0}_{L}\right\rangle +{e}^{i\theta }\left\vert {1}_{L}\right\rangle ),\\ \left\vert {\theta }_{L}^{x}\right\rangle &=&\cos \frac{\theta }{2}\left\vert {0}_{L}\right\rangle -i\sin \frac{\theta }{2}\left\vert {1}_{L}\right\rangle .\end{array}$$
(7)

Then the logical CNOT gate is applied, and finally, ancilla state is measured in logical Z or X basis. The RZ(θ) or RX(θ) gate is successfully executed only when the logical Z or X measurement results in +1; otherwise, operation RZ(2θ) or RX(2θ) needs to be applied as a compensation. Here, we simply use the post-selection strategy, that is, only retaining the cases where the measurement result is +1. Note that the ancilla states can be viewed as the result of applying RZ(θ) or RX(θ) gates to \(\left\vert {+}_{L}\right\rangle\) or \(\left\vert {0}_{L}\right\rangle\), respectively, that is why we refer to this circuit as gate teleportation circuit.

Fig. 4: Logical single-qubit rotations and characterization.
figure 4

a Gate teleportation circuits that implement single-qubit rotation operations on logical qubits. The ± sign of the rotation angle depends on the measurement results of the ancilla logical states. b, c Circuits for applying single-qubit rotations RZ(θ) and RX(θ) on the logical state \(\left\vert {\psi }_{L}\right\rangle\) based on gate teleportation, respectively. d, e Average values of Pauli operators and fidelity of the ancilla logical states \(\left\vert {\theta }_{L}^{z}\right\rangle\) and \(\left\vert {\theta }_{L}^{x}\right\rangle\) with rotation angles θ ∈ (−π, π], respectively. Scatter points and solid lines are used to distinguish experimental and simulated data. f, g Average values of Pauli operators and fidelity of the output states \({R}_{Z}(\theta )\left\vert {+}_{L}\right\rangle\) or \({R}_{X}(\theta )\left\vert {0}_{L}\right\rangle\) with rotation angles θ ∈ (−π, π], respectively.

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In the experiment, we first prepare the required ancilla logical states \(\left\vert {\theta }_{L}^{z}\right\rangle\) and \(\left\vert {\theta }_{L}^{x}\right\rangle\) with θ ∈ (−π, π] on a chain of the quantum processor (q1-q4). Then these input states are measured in XL, YL or ZL basis to obtain the expectation values of the logical Pauli operators. Subsequently, we execute the circuits in Fig. 4b, c, demonstrating the single-qubit rotation gates around the Z or X axis on the state \(\left\vert {\psi }_{L}\right\rangle =\left\vert {+}_{L}\right\rangle\) or \(\left\vert {0}_{L}\right\rangle\), respectively. The expectation values of the logical Pauli operators for the input and output states are shown in Fig. 4d–g. Using the expectation values 〈X〉, 〈Y〉, 〈Z〉, we reconstructed the density matrices, thereby calculating the fidelity of each state. The average fidelities of input states \(\left\vert {\theta }_{L}^{z}\right\rangle\) and \(\left\vert {\theta }_{L}^{x}\right\rangle\) are evaluated to be 89.0(3)%. Correspondingly, the average fidelities of the output states are 78.0(9)% and 75.0(9)%, respectively.

To characterize the fidelity of the single-qubit logical gates, it is required to construct the LPTMs of these gates. Here, we test the LPTMs of RZ(θ) and RX(θ) with θ ∈ {0, π/4, π/2, π} as examples. The input states are encoded as the logical states from the set \(\{\left\vert {+}_{L}\right\rangle ,\left\vert {-}_{L}\right\rangle ,\left\vert {0}_{L}\right\rangle ,\left\vert {i}_{L}\right\rangle \}\), and the above logical gates are applied separately. We measure the expectation values of the Pauli operators for the input and output states and construct the LPTMs for these eight logical gates accordingly (see Supplementary Note 2). The fidelities \({F}_{L}^{G}\) of these eight logical gates are estimated to be 94.4(5)%, 90.0(7)%, 87.4(7)%, 93.9(5)%, 92.1(6)%, 90.7(7)%, 89.6(7)%, 92.4(6)%, respectively.

Discussion

This work experimentally demonstrates a complete universal set of logical gates on distance-2 surface code in a superconducting processor. Particularly, logical Bell states that violates CHSH inequality have been fault-tolerantly prepared using the transversal CNOT gate. Based on the logical CNOT gate, the gate teleportation process is experimentally demonstrated to implement single-qubit rotation operations. These results reveal several significant aspects of FTQC based on the surface code in superconducting hardware.

The fidelity of logical operations are in the experiment is affected by a variety of factors. The dominant noise of our superconducting processor is the readout noise and two-qubit gate noise. Through numerical simulations, we found that the performance of logical circuits in our experiment is more sensitive to readout errors compared to gate errors. The Supplementary Note 4 presents the results of these numerical simulations and discusses the mechanisms underlying various types of noise as well as potential approaches for improvement. In addition, in the implementation of single-qubit rotation gates, the fidelity of the logical gates largely depends on the quality of the ancilla logical states in the gate teleportation circuit. In our experiment, the ancilla logical states are generated by non-fault-tolerant preparation circuits, resulting in a relatively high error rate. In a complete FTQC framework, high-fidelity ancilla logical states are typically obtained through state distillation27,49,50,51. A particularly challenging future task is to experimentally demonstrate these distillation protocols.

In our experiment, logical qubits are confined to a one-dimensional structure without measurement qubits. A natural extension is to incorporate the repeated stabilizer measurement process into our work. Achieving both the stabilizer measurement process and transversal CNOT gate typically requires a multi-layer structure or long-range entangling gates (see Supplementary Note 6). For superconducting platforms, this is regarded as a challenging long-term goal. However, we are also excited to see that they are increasingly gaining attention due to the requirements in FTQC52,53,54. Meanwhile, some prototypes of these technologies have been demonstrated recently43,44,45,46,55, indicating that they are not beyond reach.

In conclusion, our experiment enriches the possibilities for research in FTQC. First, from a near-term perspective, our work demonstrates the role of error detection codes or small-distance error-correction codes in the early FTQC era. Notably, the performance of some logical circuits in the experiment surpassed that of physical circuits. Numerical simulations further indicate that the pseudo-threshold of the experimental circuits can significantly exceed the fault-tolerant threshold (approximately 1%, see Supplementary Note 4). Second, on superconducting platforms with planar nearest-neighbor connectivity, lattice surgery is the mainstream method for logical operations56,57,58. Demonstrating transversal CNOT gates supports a hybrid scheme combining them with lattice surgery, potentially reducing the significant overhead of FTQC41,42. We have elaborated on the feasibility and benefits of this architecture in the Supplementary Note 6. Achieving this requires extending the experimental qubit layout to a multi-layer structure, which remains a long-term goal for superconducting platforms.

Methods

Fault-tolerant logical state preparation

Here, we prove that the circuits in the first two parts of Fig. 2a and b are fault-tolerant, meaning that a single-qubit error occurring at any position in the circuit can be detected without leading to a logical error. To clarify this, we note that there are two types of errors to consider: those that remain localized in a single qubit and are thus detectable by the stabilizers, and those that might affect the final state of more than one qubit. We focus on the latter type of errors, ensuring that they do not spread to become logical errors. For ease of discussion, we combine the H gates and CZ gates in the circuit into CNOT gates, focusing on the preparation of the \(\left\vert {0}_{L}\right\rangle\) and \(\left\vert {+}_{L}\right\rangle\) states, resulting in the circuit shown in Fig. 5. This simplification does not affect the fault-tolerance of the original circuits.

Fig. 5: Equivalent logical state fault-tolerant preparation circuit.
figure 5

The circuits are simplified to a composition of CNOT and H gates, with fault tolerance equivalent to the original circuits. The possible X (blue) or Z (yellow) errors that could propagate are shown. a Fault-tolerant (FT) preparation circuit for \(\left\vert 0\right\rangle\). b Fault-tolerant (FT) preparation circuit for \(\left\vert +\right\rangle\).

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For the \(\left\vert {0}_{L}\right\rangle\) state preparation circuit, we only need to consider the Pauli X errors in the circuit, as any logical ZL error produced is trivial for the \(\left\vert 0/{1}_{L}\right\rangle\) state up to a global phase. We mark the locations of all possible single-qubit Pauli X errors (shown as blue X in Fig. 5a). The leftmost X error affects qubits 1 through 4 as X1X2X3X4, which is a stabilizer. The second and third X errors affect qubits 2 and 3 as X2X3 and qubits 1 and 4 as X1X4, respectively. These errors anti-commute with the stabilizers Z1Z2 and Z3Z4, and thus they will be detected by the stabilizer measurements. This proves that no single-qubit Pauli X error at any position in the circuit can spread to become a logical XL error.

Similarly, in the \(\left\vert {+}_{L}\right\rangle\) state preparation circuit, we consider the possible Pauli Z errors. The two possible spreading Pauli Z errors (yellow Z in Fig. 5b) affect qubits 1 and 2 as Z1Z2 and qubits 3 and 4 as Z3Z4, which are the two stabilizers of this code. Since all these errors can be detected or lead to a stabilizer operator, we have demonstrated the fault-tolerance of these two encoding circuits.

Logical Pauli transfer matrix (LPTM)

The Pauli transfer matrix (PTM) describes a quantum process on the components of the density matrix represented in the basis of Pauli operators6,59,60,61. For a d-dimensional Hilbert space, a PTM \({\mathcal{R}}\) is a linear transformation matrix from the expectation values pi = 〈Pi〉 of the Pauli operators Pi in the input state to the expectation values \({p}_{j}^{{\prime} }\) in the output state:

$${p}_{j}^{{\prime} }=\sum _{i}{{\mathcal{R}}}_{ij}{p}_{i}.$$
(8)

In our experiment, Pi belongs to \({\{{I}_{L},{X}_{L},{Y}_{L},{Z}_{L}\}}^{\otimes 2}\) and {IL, XL, YL, ZL} for the cases d = 4 and d = 2, respectively. To construct the LPTMs of the logical quantum gates in the main text, we use input states from the complete set \({\{\left\vert {+}_{L}\right\rangle ,\left\vert {-}_{L}\right\rangle ,\left\vert {0}_{L}\right\rangle ,\left\vert {i}_{L}\right\rangle \}}^{\otimes 2}\) (for the logical CNOT gate) or \(\{\left\vert {+}_{L}\right\rangle ,\left\vert {-}_{L}\right\rangle ,\left\vert {0}_{L}\right\rangle ,\left\vert {i}_{L}\right\rangle \}\) (for the logical single-qubit gates). The density matrices of the input and output states are obtained through logical state tomography, and the expectation values pi and \({p}_{j}^{{\prime} }\) are then calculated. The inverse of the expectation value matrix yields the raw result \({{\mathcal{R}}}^{{\rm{raw}}}\). However, \({{\mathcal{R}}}^{{\rm{raw}}}\) may not satisfy the conditions of a physical channel, i.e., being completely positive and trace-preserving6. Therefore, using the techniques in ref. 31, \({{\mathcal{R}}}^{{\rm{raw}}}\) is transformed into the Choi state representation:

$${\rho }_{{\rm{choi}}}=\frac{1}{{d}^{2}}\sum _{ij}{{\mathcal{R}}}_{ij}^{{\rm{raw}}}{P}_{j}^{T}\otimes {P}_{i}.$$
(9)

We then optimize ρ under the following objective function and constraints:

$$\begin{array}{rcl}{\rm{minimize}}&&\sum\limits_{i,j}{\left\vert {\rm{Tr}}(\rho {P}_{j}^{T}\otimes {P}_{i})-{{\mathcal{R}}}_{ij}^{{\rm{raw}}}\right\vert }^{2},\\ {\rm{subject}}\,{\rm{to}}&&\rho \ge 0,{\rm{Tr}}(\rho )=1,{{\rm{Tr}}}_{1}(\rho )=\frac{1}{2}{\mathbb{1}},\end{array}$$
(10)

where \({{\rm{Tr}}}_{1}\) is the partial trace over the left half subsystem. Using the convex optimization package cvxpy, we obtain the optimal result ρopt. The corresponding LPTM \({\mathcal{R}}\) is

$${{\mathcal{R}}}_{ij}={\rm{Tr}}({\rho }_{{\rm{opt}}}{P}_{j}^{T}\otimes {P}_{i})$$
(11)

and the fidelity of the logical gate is

$${F}_{L}^{G}=\frac{{\rm{Tr}}({{\mathcal{R}}}^{\dagger }{{\mathcal{R}}}_{{\rm{ideal}}})+d}{{d}^{2}+d},$$
(12)

where \({{\mathcal{R}}}_{{\rm{ideal}}}\) is the ideal LPTM of the logical gate?. In our experiment, we constructed the LPTMs for the logical CNOT gate and eight logical single-qubit gates. The specific details of these LPTMs can be found in the Supplementary Note 2.

Quantum state tomography

Quantum state tomography62,63,64 reconstructs the density matrix of an unknown quantum state by measuring some observables. In our experiment, we measure 4n − 1 Pauli operators of the logical qubits, where n is the number of logical qubits. Assuming the expectation values of these Pauli operators are pi = 〈Pi〉, where \({P}_{i}\in {\{{I}_{L},{X}_{L},{Y}_{L},{Z}_{L}\}}^{\otimes n}/\{{I}_{L}^{\otimes n}\}\), the density matrix is reconstructed as:

$${\rho }_{L,0}=\mathop{\sum }\limits_{i=0}^{{4}^{n}-1}\frac{{p}_{i}{P}_{i}}{{2}^{n}},$$

with p0 = 1 and \({P}_{0}={I}_{L}^{\otimes n}\). Such a density matrix ρL,0 may not satisfy the physicality characteristics of a quantum state. Therefore, we use maximum likelihood estimation65,66 to construct the logical density matrix ρL. Specifically, the objective function to minimize is

$$\sum _{i}| {\rm{Tr}}({\rho }_{L}{P}_{i})-{p}_{i}{| }^{2},$$
(13)

subject to \({\rm{Tr}}({\rho }_{L})=1\), and ρL ≥ 0. This process is implemented also using the convex optimization package cvxpy. Likewise, we also apply state tomography to physical states for constructing the density operators of states \(\left\vert 0\right\rangle\), \(\left\vert 1\right\rangle\), \(\left\vert +\right\rangle\), \(\left\vert -\right\rangle\) and four Bell states, which is done for comparison with the logical state density matrices. These results are shown in the Supplementary Note 2.