Fig. 3: Logical CNOT gate and Bell state characterization.
a Circuit of the logical CNOT gate implemented transversally. b, c Circuit for applying a logical CNOT gate on arbitrary logical states \(\left\vert {\psi }_{L}\right\rangle\) and \(\left\vert {\varphi }_{L}\right\rangle\), and the circuit for fault-tolerant preparation of Bell states, respectively. The blocks represent logical state preparation circuits and the logical CNOT gate. The upper half of the logical CNOT block corresponds to the control logical qubit, while the lower half corresponds to the target logical qubit. d Density matrices and fidelities of the four logical Bell states prepared fault-tolerantly in the experiment. e Average fidelity and post-selection (PS) rates of four logical Bell states when measuring XL ⊗ XL, YL ⊗ YL and ZL ⊗ ZL in experiments and simulations.
