Table 2 Comparison of the fidelities between fault-tolerant prepared logical states and physical states (including preparation and characterization) in the experiment

From: Demonstrating a universal logical gate set in error-detecting surface codes on a superconducting quantum processor

State

Logical state fidelity

Physical state fidelity

\(\left\vert {0}_{L}\right\rangle /\left\vert 0\right\rangle\)

97.9(2)%

96.9(3)%

\(\left\vert {1}_{L}\right\rangle /\left\vert 1\right\rangle\)

98.0(2)%

90.8(6)%

\(\left\vert {+}_{L}\right\rangle /\left\vert +\right\rangle\)

97.7(2)%

94.8(4)%

\(\left\vert {-}_{L}\right\rangle /\left\vert -\right\rangle\)

97.8(2)%

93.6(5)%

Four Bell states

79.5(5)%

74.4(9)%

 

79.5(5)%

74.2(9)%

 

79.4(5)%

74.5(9)%

 

79.4(5)%

74.2(9)%