Extended Data Fig. 4: SiO2 spacer-based low-fringing-field FETs.
From: Gate structuring on n-type bilayer MoS2 field-effect transistors for ultrahigh current density
a, Schematics showing SiO2 spacer fabrication process. Source drain electrodes were fabricated by patterning a photoresist with a large undercut, followed by Au evaporation, subsequent SiO2 evaporation, and a single lift off step, resulting in a SiO2 spacer that covers the Au contacts. b, Comparison of the structure near the original contact (top) and the modified structure with an SiO2 spacer (bottom). Because the dielectric constant of SiO2 is lower than that of HfOx, the fringing capacitance associated with the SiO2 spacer (Cf, SiO2) is smaller than the fringing capacitance that arises from the HfOx filled field (Cf, HfOx). c, Cross sectional TEM image of a fabricated MoS2 FET that incorporates the SiO2 spacer. d,e, Transfer curves of the reference structure without a spacer: back gate configuration (d) and dual gate configuration (e). f,g, Transfer curves of the FETs with a SiO2 spacer: back gate configuration (f) and dual gate configuration (g). Insertion of the spacer reduces the fringing field, resulting in higher current and improved variation. h, Comparison of Ion at Vgs = 3 V extracted from the preceding transfer curves. After SiO2 spacer insertion, both the back‑gate and dual‑gate configurations exhibit a pronounced increase in Ion. All data in this figure are presented as mean values +/- standard deviation.
