Abstract
The foundry industry and academia are confronting the limits of Moore’s Law scaling for logic transistors. Silicon field‑effect transistors (FETs) now rely on gate‑all‑around structures and ultrathin channels, even at the cost of decreased carrier mobility and complex fabrication processes. Two‑dimensional (2D) semiconductors offer a promising alternative because they retain their crystalline quality at atomic thicknesses. Nonetheless, whether they truly exhibit higher performance than silicon remains questionable. Here, by implementing a dual‑gate structure on bilayer MoS2 FETs, we mitigate the fringing‑field barrier created by the elevated top contact and achieve high carrier densities without increasing fabrication complexity. Simulations and statistical analysis confirm that the dual‑gate compensates the fringe field, enabling a drain current of 1.55 mA µm−1 even with conventional gold contacts. Quantum‑transport simulation indicates that, with further gate‑length and equivalent‑oxide‑thickness scaling, the on-state current can reach levels comparable to silicon FETs at the 3-nm node, and monolithic 3D integration can extend the applicability of dual‑gate 2D transistors to future logic technologies.
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Data availability
Source data are provided with this paper. Any additional data supporting the conclusions of this work can be obtained from the corresponding authors upon request.
Code availability
The Python code (v.3.8.5) used for the statistical analysis of FETs in this study is available from the corresponding authors upon request.
References
Cao, W. et al. The future transistors. Nature 620, 501–515 (2023).
Ferain, I., Colinge, C. A. & Colinge, J.-P. Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors. Nature 479, 310–316 (2011).
Liu, Y. et al. Promises and prospects of two-dimensional transistors. Nature 591, 43–53 (2021).
International Roadmap for Devices and Systems https://irds.ieee.org/editions/2022 (IEEE, 2022).
Jeong, J. et al. World’s first GAA 3nm foundry platform technology (SF3) with novel multi-bridge-channel-FET (MBCFETTM) process. In 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) 1–2 (IEEE, 2023); https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185353
Chou, B.-J. et al. High-performance monolayer MoS2 nanosheet GAA transistor. Nanotechnology 35, 125204 (2024).
O’Brien, K. P. et al. Advancing 2D monolayer CMOS through contact, channel and interface engineering. In 2021 IEEE International Electron Devices Meeting (IEDM) 7.1.1–7.1.4 (IEEE, 2021); https://doi.org/10.1109/IEDM19574.2021.9720651
O’Brien, K. P. et al. Process integration and future outlook of 2D transistors. Nat. Commun. 14, 6400 (2023).
Kim, K. S. et al. Non-epitaxial single-crystal 2D material growth by geometric confinement. Nature 614, 88–94 (2023).
Kim, K. S. et al. Growth-based monolithic 3D integration of single-crystal 2D semiconductors. Nature 636, 615–621 (2024).
Moon, D. et al. Hypotaxy of wafer-scale single-crystal transition metal dichalcogenides. Nature https://doi.org/10.1038/s41586-024-08492-9 (2025).
Shen, P.-C. et al. Ultralow contact resistance between semimetal and monolayer semiconductors. Nature 593, 211–217 (2021).
Li, W. et al. Approaching the quantum limit in two-dimensional semiconductor contacts. Nature 613, 274–279 (2023).
Ko, J.-S. et al. Ultrathin gate dielectric enabled by nanofog aluminum oxide on monolayer MoS2. In ESSDERC 2023—IEEE 53rd European Solid-State Device Research Conference (ESSDERC) 1–4 (IEEE, 2023) https://doi.org/10.1109/ESSDERC59256.2023.10268527
Radisavljevic, B., Radenovic, A., Brivio, J., Giacometti, V. & Kis, A. Single-layer MoS2 transistors. Nat. Nanotechnol. 6, 147–150 (2011).
Ugeda, M. M. et al. Giant bandgap renormalization and excitonic effects in a monolayer transition metal dichalcogenide semiconductor. Nat. Mater. 13, 1091–1095 (2014).
Kwon, J. et al. Thickness-dependent Schottky barrier height of MoS2 field-effect transistors. Nanoscale 9, 6151–6157 (2017).
Zhang, S. et al. Wafer-scale transferred multilayer MoS2 for high performance field effect transistors. Nanotechnology 30, 174002 (2019).
Bennett, R. K. A. & Pop, E. How do quantum effects influence the capacitance and carrier density of monolayer MoS2 transistors? Nano Lett. 23, 1666–1672 (2023).
Kim, K. S. et al. The future of two-dimensional semiconductors beyond Moore’s law. Nat. Nanotechnol. 19, 895–906 (2024).
Kita, Y. et al. Systematic study on work-function-shift in metal/Hf-based high-k gate stacks. Appl. Phys. Lett. 94, 122905 (2009).
Guo, Y. et al. Field-effect at electrical contacts to two-dimensional materials. Nano Res. 14, 4894–4900 (2021).
Lv, J., Shen, Z., Meng, D., Peng, L.-M. & Qiu, C. High-performance dual-gate transistors based on aligned carbon nanotubes. ACS Appl. Mater. Interfaces 16, 58864–58871 (2024).
Illarionov, Y. Y. et al. Insulators for 2D nanoelectronics: the gap to bridge. Nat. Commun. 11, 3385 (2020).
Pasadas, F. et al. Large-signal model of 2DFETs: compact modeling of terminal charges and intrinsic capacitances. npj 2D Mater. Appl. 3, 47 (2019).
Fan, D. et al. Two-dimensional semiconductor integrated circuits operating at gigahertz frequencies. Nat. Electron. 6, 879–887 (2023).
Silvestri, L. et al. Hierarchical modeling for TCAD simulation of short-channel 2D material-based FETs. Solid State Electron. 200, 108533 (2023).
Liu, L. et al. Uniform nucleation and epitaxy of bilayer molybdenum disulfide on sapphire. Nature 605, 69–75 (2022).
Hwangbo, S., Hu, L., Hoang, A. T., Choi, J. Y. & Ahn, J.-H. Wafer-scale monolithic integration of full-colour micro-LED display using MoS2 transistor. Nat. Nanotechnol. 17, 500–506 (2022).
Li, H. et al. From bulk to monolayer MoS2: evolution of Raman scattering. Adv. Funct. Mater. 22, 1385–1390 (2012).
Ma, N. & Jena, D. Carrier statistics and quantum capacitance effects on mobility extraction in two-dimensional crystal semiconductor field-effect transistors. 2D Mater. 2, 015003 (2015).
Jiang, J. et al. Yttrium-doping-induced metallization of molybdenum disulfide for ohmic contacts in two-dimensional transistors. Nat. Electron. https://doi.org/10.1038/s41928-024-01176-2 (2024).
Chou, A.-S. et al. High on-current 2D nFET of 390 μA/μm at VDS = 1 V using monolayer CVD MoS2 without intentional doping. In 2020 IEEE Symposium on VLSI Technology 1–2 (IEEE, 2020); https://doi.org/10.1109/VLSITechnology18217.2020.9265040
Chou, A.-S. et al. Antimony semimetal contact with enhanced thermal stability for high performance 2D electronics. In 2021 IEEE International Electron Devices Meeting (IEDM) 7.2.1–7.2.4 (IEEE, 2021); https://doi.org/10.1109/IEDM19574.2021.9720608
Chou, A.-S. et al. High on-state current in chemical vapor deposited monolayer MoS2 nFETs with Sn ohmic contacts. IEEE Electron Device Lett. 42, 272–275 (2021).
Li, L. et al. Epitaxy of wafer-scale single-crystal MoS2 monolayer via buffer layer control. Nat. Commun. 15, 1825 (2024).
Xiong, X. et al. Demonstration of vertically-stacked CVD monolayer channels: MoS2 nanosheets GAA-FET with Ion > 700 µA/µm and MoS2/WSe2 CFET. In 2021 IEEE International Electron Devices Meeting (IEDM) 7.5.1–7.5.4 (IEEE, 2021); https://doi.org/10.1109/IEDM19574.2021.9720533
Zou, T. et al. High-performance solution-processed 2D p-type WSe2 transistors and circuits through molecular doping. Adv. Mater. 35, 2208934 (2023).
Li, N. et al. Large-scale flexible and transparent electronics based on monolayer molybdenum disulfide field-effect transistors. Nat. Electron. 3, 711–717 (2020).
Cheng, K.-L. et al. A highly scaled, high performance 45 nm bulk logic CMOS technology with 0.242 μm2 SRAM cell. In 2007 IEEE International Electron Devices Meeting 243–246 (IEEE, 2007); https://doi.org/10.1109/IEDM.2007.4418913
Mistry, K. et al. A 45 nm logic technology with high-k + metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging. In 2007 IEEE International Electron Devices Meeting 247–250 (IEEE, 2007); https://doi.org/10.1109/IEDM.2007.4418914
Pal, A., Chavan, T., Jabbour, J., Cao, W. & Banerjee, K. Three-dimensional transistors with two-dimensional semiconductors for future CMOS scaling. Nat. Electron. 7, 1147–1157 (2024).
Tang, J. et al. Low-power 2D gate-all-around logics via epitaxial monolithic 3D integration. Nat. Mater. https://doi.org/10.1038/s41563-025-02117-w (2025).
English, C. D., Shine, G., Dorgan, V. E., Saraswat, K. C. & Pop, E. Improved contacts to MoS2 transistors by ultra-high vacuum metal deposition. Nano Lett. 16, 3824–3830 (2016).
Kim, C. et al. Transfer free 2D CMOS multi bridge channel FET. In 2024 IEEE International Electron Devices Meeting (IEDM) 1–4 (IEEE, 2024); https://doi.org/10.1109/IEDM50854.2024.10873503
Mirabelli, G., Hurley, P. K. & Duffy, R. Physics-based modelling of MoS2: the layered structure concept. Semicond. Sci. Technol. 34, 055015 (2019).
Donetti, L. et al. Towards a DFT-based layered model for TCAD simulations of MoS2. Solid State Electron. 197, 108437 (2022).
Stanojević, Z. et al. Nano device simulator—a practical subband-BTE solver for path-finding and DTCO. IEEE Trans. Electron. Devices 68, 5400–5406 (2021).
Park, H.-H. et al. Toward more realistic NEGF simulations of vertically stacked multiple SiNW FETs. In 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 206–209 (IEEE, 2018); https://doi.org/10.1109/SISPAD.2018.8551692
Kim, K. Y. et al. Quantum transport through a constriction in nanosheet gate-all-around transistors. Commun. Eng. 4, 92 (2025).
J. Park et al. First demonstration of 3-dimensional stacked FET with top/bottom source-drain isolation and stacked n/p metal gate. In 2023 International Electron Devices Meeting (IEDM) 1–4 (IEEE, 2023); https://doi.org/10.1109/IEDM45741.2023.10413694
Kasamatsu, S., Watanabe, S. & Han, S. Orbital-separation approach for consideration of finite electric bias within density-functional total-energy formalism. Phys. Rev. B 84, 085120 (2011).
Kasamatsu, S., Watanabe, S. & Han, S. First-principles calculation of charged capacitors under open-circuit conditions using the orbital-separation approach. Phys. Rev. B 92, 115124 (2015).
Seol, M. et al. High-throughput growth of wafer-scale monolayer transition metal dichalcogenide via vertical Ostwald ripening. Adv. Mater. 32, 2003542 (2020).
Kwon, J. et al. 200-mm-wafer-scale integration of polycrystalline molybdenum disulfide transistors. Nat. Electron. https://doi.org/10.1038/s41928-024-01158-4 (2024).
Nguyen, V. L. et al. Wafer-scale integration of transition metal dichalcogenide field-effect transistors using adhesion lithography. Nat. Electron. 6, 146–153 (2023).
Kwak, I. et al. Low interface trap density in scaled bilayer gate oxides on 2D materials via nanofog low temperature atomic layer deposition. Appl. Surf. Sci. 463, 758–766 (2019).
International Technology Roadmap for Semiconductors (ITRS) 2007 Edition. https://www.semiconductors.org/resources/2007-international-technology-roadmap-for-semiconductors-itrs/, (Semiconductor Industry Association, 2007).
Acknowledgements
This work was supported by Samsung Advanced Institute of Technology, Samsung Electronics Co., Ltd.
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J. Kwon, K.Y.K., D.J., K.-E.B., M.S. and J. Kim conceived the project and defined the research strategy. J. Kwon designed, fabricated and measured all wafer‑scale devices, performed the data analysis and drafted the paper. K.Y.K. carried out all TCAD/NEGF simulations, developed the device‑level models, supervised the simulation work and contributed to paper preparation. D.J. interpreted the simulation results, helped shape the logical flow of the paper and participated in writing. M.S.Y. and A.J. were responsible for the wafer‑scale growth of monolayer and bilayer MoS2 films by MOCVD. D.-S.K. performed TEM imaging and analysis. Y.H. performed quantum‑capacitance simulations. H.R. participated in the fabrication of low‑k spacer devices. W.I.C. carried out DFT‑based calculations of the MoS2 electronic structure. Y.C. led the discussion on MoS2 transport mechanisms. C.K. contributed to the discussion of the experimental results. E.Y. acquired the SEM images and assisted with structural characterization. E.K.L. analysed the electrical‑measurement data and led the discussion of these results. C‑S.L. and S.W.K. provided the overall direction of the research, gave technical guidance and reviewed the paper. U.K. and D.S.K. discussed the simulation strategy, guided its development and supervised K.Y.K. S.K.L. supervised D.J. and led the discussion on future logic technologies. K.‑E.B., M.S. and J. Kim supervised J. Kwon, contributed to the interpretation of the results and co‑wrote the paper. All authors discussed the results, contributed to the interpretation of the data and approved the final version of the paper.
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Extended data
Extended Data Fig. 1 Transfer curves (Ids – Vgs) simulated using TCAD.
a,b, Transfer curves of single gate (green) and dual gate (navy) monolayer MoS2 FETs plotted on both semi-log (a) and linear (b) scales. c,d, Transfer curves of single gate (orange) and dual gate (wine) bilayer MoS2 FETs plotted on both semi-log (c) and linear (d) scales.
Extended Data Fig. 2 Raman map images of large area MoS2 films.
a, Image mapping the ratio of A peak intensity (IA) of monolayer MoS2 to Si peak intensity (ISi). b, Image mapping the distance between the E peak position (PE) and A peak position (PA) of monolayer MoS2. c, Image mapping the ratio of IA of bilayer MoS2 to ISi. d, Image mapping the distance between the PE and PA of bilayer MoS2. Only the 100 mm×100 mm region is mapped, as the device fabrication area was confined to the 100 mm centre region of the wafer.
Extended Data Fig. 3 Evaluation of 200-mm-wafer-scale long channel (Lch > 500 nm) FETs based on bilayer MoS2.
a, Transfer curves (σsh – Vgs) of back gate (red), top gate (blue), and dual gate (green) MoS2 FETs fabricated across the entire 200-mm wafer. b,c, Statistical distribution of Ion and subthreshold swing (SS) for back gate (red), top gate (blue), and dual gate (green) configurations. In dual gate configurations, not only Ion and SS have substantially improved, but the variance has also been greatly reduced. Here, the numbers of measured back‑gate, top‑gate, and dual‑gate FETs are 40, 42, and 48, respectively. The box represents the 25 %–75 % range, the line in the middle indicates the median, and the circle denotes the mean value. d, Statistical analysis of field-effect (FE) mobility of dual-gate FETs as a function of Lch. The consistent FE mobility values across different Lch values indicate that the RC has sufficiently decreased. e, Threshold voltage (Vth) of dual-gate FETs extracted using the linear extrapolation method (hollow hexagon) from the transfer curve and the Vth extracted using the constant current method (filled hexagon). The constant current value used was 50 nA. The number of devices for d and e by Lch are: 115 devices for 500 nm, 60 for 1 µm, 34 for 2 µm, 35 for 5 µm, 36 for 10 µm, and 35 for 20 µm. Data in d, e are presented as mean values +/- standard deviation. f. A wafer map showing die-by-die device yield for the dual gate structure, demonstrating a high yield of 99.7%.
Extended Data Fig. 4 SiO2 spacer-based low-fringing-field FETs.
a, Schematics showing SiO2 spacer fabrication process. Source drain electrodes were fabricated by patterning a photoresist with a large undercut, followed by Au evaporation, subsequent SiO2 evaporation, and a single lift off step, resulting in a SiO2 spacer that covers the Au contacts. b, Comparison of the structure near the original contact (top) and the modified structure with an SiO2 spacer (bottom). Because the dielectric constant of SiO2 is lower than that of HfOx, the fringing capacitance associated with the SiO2 spacer (Cf, SiO2) is smaller than the fringing capacitance that arises from the HfOx filled field (Cf, HfOx). c, Cross sectional TEM image of a fabricated MoS2 FET that incorporates the SiO2 spacer. d,e, Transfer curves of the reference structure without a spacer: back gate configuration (d) and dual gate configuration (e). f,g, Transfer curves of the FETs with a SiO2 spacer: back gate configuration (f) and dual gate configuration (g). Insertion of the spacer reduces the fringing field, resulting in higher current and improved variation. h, Comparison of Ion at Vgs = 3 V extracted from the preceding transfer curves. After SiO2 spacer insertion, both the back‑gate and dual‑gate configurations exhibit a pronounced increase in Ion. All data in this figure are presented as mean values +/- standard deviation.
Extended Data Fig. 5 Transfer length method (TLM) of MoS2 FETs.
a, Total resistance (Rtot) as a function of channel length (Lch) for single gate and monolayer MoS2 FET at a planar carrier density (n2D) of 7.69 ×1012 cm−2. The number of devices for each Lch is as follows: 10 devices for 30 nm, 52 for 40 nm, 67 for 50 nm, 16 each for 60, 70, 80, 150, 200, 250, and 300 nm, and 15 for 100 nm. b, Same plot for dual gate and monolayer MoS2 FET at n2D of 1.51 ×1013 cm−2. 13 devices for 30 nm, 69 for 40 nm, 85 for 50 nm, and 18 each for 60, 70, 80, 100, 150, 200, 250, and 300 nm. c, Same plot for single gate and bilayer MoS2 FET at n2D of 1.04 ×1013 cm−2. 5 devices for 30 nm, 32 for 40 nm, 55 for 50 nm, 14 for 60 nm, 15 for 70 nm, 14 for 80 nm, 14 for 100 nm, 16 for 150 nm, 16 for 200 nm, 16 for 250 nm, and 17 for 300 nm. d, Same plot for dual gate and bilayer MoS2 FET at n2D of 1.7 ×1013 cm−2. 13 devices for 30 nm, 57 for 40 nm, 78 for 50 nm, 16 for 60 nm, 15 for 70 nm, 16 for 80 nm, 17 for 100 nm, 17 for 150 nm, 17 for 200 nm, 18 for 250 nm, and 17 for 300 nm. All data in this figure are presented as mean values +/- standard deviation.
Extended Data Fig. 6 Variation in transfer curves of dual-gate MoS2 FETs with Lg shrinkage.
a, NEGF simulation models of bilayer MoS2 dual-gate FETs with Lg = 30 nm, 12 nm, and 5 nm, from top to bottom. The bilayer MoS2 was modelled with a vdW gap between the two MoS2 layers. b, Transfer curves at Vds = 0.7 V for Lg = 30 nm (pink), 12 nm (purple), and 5 nm (navy blue) calculated by quantum simulation. As Lg decreases to 5 nm, the transfer curve (navy blue) becomes increasingly similar to the ballistic transport-assumed transfer curve (light blue), indicating a higher proportion of ballistic transport under shorter Lg.
Extended Data Fig. 7 Variation in transfer curves of Si FETs with Lg shrinkage.
a, NEGF simulation models of Si GAAFETs with Lg = 12 nm and 5 nm, from top to bottom. The thickness of the Si channel is fixed to 4 nm. b, Transfer curves at Vds = 0.7 V for 12 nm (pink), and 5 nm (orange) calculated by quantum simulation. Unlike MoS2, Si exhibits a notable degradation in SS due to the short-channel effect as Lg is reduced to 5 nm.
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Kwon, J., Kim, K.Y., Jang, D. et al. Gate structuring on n-type bilayer MoS2 field-effect transistors for ultrahigh current density. Nat. Mater. (2026). https://doi.org/10.1038/s41563-025-02452-y
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DOI: https://doi.org/10.1038/s41563-025-02452-y
