Extended Data Fig. 5: Cycle-to-cycle test.
From: Sb-contacted MoS2 flash memory for analogue in-memory searches
(a) 1000-time program/erase (P/E) cycling experiment in DC mode, with program voltage of 13 V and erase voltage of -6V. (b) Vth drift for each cycle. (c) 105-time P/E cycling experiment in pulse mode, with pulse amplitude of 10 V for programming and -10V for erasing, pulse width of 100 ms. We observed some Vth drift over cycling. This is characteristic of an open-loop cycling test, where fixed programming/erasing conditions are applied without feedback. This drift is also exacerbated when operating near equipment limitations for pulse amplitude that necessitate longer pulse widths. In practical applications, such drift can be effectively managed. Closed-loop adaptive schemes, such as iterative program-and-verify algorithms, can be used to precisely set and maintain desired Vth levels, compensating for inherent device variations and cycling-induced shifts.
