Abstract
The explosion of artificial intelligence and edge devices has exposed a critical bottleneck in traditional hardware: the slow data transfer between memory and processing. Content-addressable memories offer a promising solution by processing information directly within the memory, but existing implementations using static random-access memory and, more recently, those using emerging non-volatile memories are constrained by the performance of silicon transistors. Here we introduce an analogue content-addressable memory utilizing atomically thin two-dimensional MoS2 flash memories with semimetal antimony contacts. Our device achieves a high read-out current (60 μA μm−1) and large ON/OFF ratios (>109) in two-dimensional flash memories. These breakthroughs have led to very low energy consumption (under 0.1 fJ per search per cell) and latency (36 ps) during analogue in-memory search operations within our 8 × 16 analogue content-addressable memory array, featuring 256 MoS2 flash memory devices. We have also successfully demonstrated analogue Hamming distance computing for k-nearest neighbour classification, showcasing high accuracy, high energy efficiency and low latency for machine learning applications. This research highlights the transformative potential of two-dimensional materials in overcoming current hardware limitations, enabling more efficient and scalable computing solutions in intelligent edge devices.
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The data supporting this study’s findings are available from the corresponding authors on request. Source data are provided with this paper.
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Acknowledgements
This work was supported in part by Research Grants Council (RGC) of Hong Kong SAR (27210321 (C.L.), C7003-24Y (C.L.), C1009-22GF (C.L.), T45-701/22-R (C.L.), T46-705/23-R (L.-J.L.), CRS_PolyU502/22 (L.-J.L.), AoE/P-701/20 (D.-K.K.), the National Natural Science Foundation of China (62122005 (C.L.)); ACCESS—an InnoHK center by ITC (C.L.), MIND project (MINDXZ202503 (C.L.)), and Croucher Foundation (C.L.). L.-J.L. acknowledges support from the National Research Foundation Singapore (NRF Professorship NRF-P2025-002 (L.-J.L.)). This fabrication was performed in part at the Central Fabrication Laboratory (CFL) at HKU and the Nanosystem Fabrication Facility of HKUST.
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C.L. and L.-J.L. conceived the idea and supervised the project. G.G., B.W., Z.D., M.J., R.Q. and H.X. contributed to the device fabrication, measurements and data analysis. B.W. performed the simulations and data analysis. G.G., Y.C., D.Z., P.S.Y. and Q.L. performed the ALD of Al2O3 and HfO2. G.G., N.Y. and Y.W. performed the thermal deposition of Sb/Au, chemical vapour deposition growth of MoS2 and Raman characterization. G.G., B.W. and C.L. wrote and revised the manuscript with input from all authors. All authors discussed the results and provided comments on the manuscript.
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Extended data
Extended Data Fig. 1 Temperature-dependent electrical characteristics and extracted Schottky barrier.
(a) Transfer characteristic curves of the MoS2 flash memory (LCH = 200 nm) measured at low temperature. (b) Output characteristic curves of the MoS2 flash memory measured at 10 K, VG = -6 V ~ 10 V. The linear IV curves at small bias voltage indicate an ideal Ohmic contact of Sb–MoS2. (c) Arrhenius plots of the ohmic Sb–MoS2 flash memory at different VG = -5 V ~ 7 V and VD = 0.1 V. (d) The extracted energy barrier vs VG, showing a negligible Schottky barrier for Sb–MoS2 flash memory at flat band state.
Extended Data Fig. 2 The extracted contact resistance Rc and benchmark.
(a) Output characteristic curves of Sb/Au Ohmic contact and Cr/Au Schottky contact devices. When using Cr/Au as contact electrodes, there exists an unavoidable Schottky barrier due to the strong Fermi level pinning at the contact interface, which usually induces non-linear output characteristic curves. In comparison, the Sb/Au contact device not only shows linear output characteristic curves, but also much larger output current. (b) Transfer characteristic curves of a typical TLM with channel length LCH ranging from 200 nm to 500 nm and VD = 1 V. Inset shows scanning electron microscope image of the Sb/Au contact devices with a TLM structure. MoS2 film was patterned into a strip with a width of 1.5 μm. Scale bar: 2 μm. (c) Rc extraction using the TLM method under different carrier densities. The y-intercept represents 2Rc = 800~1400 Ω μm, suggesting a Rc ranging from 400 Ω μm to 700 Ω μm at different carrier densities ranging from 0.19 ×1013 cm−2 to 0.77 ×1013 cm−2. (d) Rc as a function of carrier density n2D (n2D = Cox (VG – Vth)/q) for monolayer MoS2 with various contact metals or semimetals in the literature. The grey dashed line represents the quantum limit for Rc, πh/(4q2kF) ≈ 0.036(n2D)−0.5 kΩ μm, where h is Planck’s constant, q is the elementary charge, kF is the Fermi wavevector. The state-of-the-art Sb/Au-MoS2 FET was reported to approach the quantum limit in 2D semiconductor contacts26. We first reported the Sb/Au-MoS2 flash memory with ultra-small contact resistance, while at a lower carrier density, surpassing most metal contact FETs at a similar carrier density.
Extended Data Fig. 3 More data and statistics.
(a) Transfer characteristic curves of 1024 devices in four 16×16 arrays (LCH = 500 nm). (b) Statistical histograms and Gaussian fits of maximum readout current (VG = 3 V, VD = 1 V), showing a good batch-to-batch uniformity.
Extended Data Fig. 4 Selective erasing/programming of MoS2 flash memory array.
(a) Selectively erase a single cell in the same column. (b) The distribution of readout current of 96 devices within a 6x16 array, read at VG = -1.2 V and VD = 1 V. 32 devices were selectively programmed, through the readout current, three letters of “HKU” can be observed.
Extended Data Fig. 5 Cycle-to-cycle test.
(a) 1000-time program/erase (P/E) cycling experiment in DC mode, with program voltage of 13 V and erase voltage of -6V. (b) Vth drift for each cycle. (c) 105-time P/E cycling experiment in pulse mode, with pulse amplitude of 10 V for programming and -10V for erasing, pulse width of 100 ms. We observed some Vth drift over cycling. This is characteristic of an open-loop cycling test, where fixed programming/erasing conditions are applied without feedback. This drift is also exacerbated when operating near equipment limitations for pulse amplitude that necessitate longer pulse widths. In practical applications, such drift can be effectively managed. Closed-loop adaptive schemes, such as iterative program-and-verify algorithms, can be used to precisely set and maintain desired Vth levels, compensating for inherent device variations and cycling-induced shifts.
Extended Data Fig. 6 Long-term reliability and retention.
(a) The transfer characteristic curves of the original state and programmed state. The device can still be programmed even after 30 months. (b) Retention measurement over 104 s (3 h), and (c) over 15 h after 30 months.
Extended Data Fig. 7 Search operation for 1-bit to 7-bit mismatch.
(a) Programmed search boundaries of 8 analog CAM cells in the same row during search operations for 1-bit to 7-bit mismatch (bottom to top). Some cell curves appear outside the visible range as they are programmed to mismatch everything. A 0.1 V signal was applied to all DLs as input data. The cells were programmed with different search ranges to create controlled mismatch scenarios: The experimental searching boundaries for each cellb, where red traces indicate mismatch bits (high discharge current at 0.1 V input), while blue traces indicate match bits (low discharge current at 0.1 V input). (b) Input and stored data during search operations for 1-bit to 7-bit mismatch. (c) Experimental discharge behaviors observed during search operations for 1-bit to 7-bit mismatch.
Extended Data Fig. 8 TCAM used classification applications using k-nearest neighbor (KNN, k = 3) search in analog CAM and the inference latency comparison with CPU.
(a) The embedded digital data after the binarization encoding, and distance computing results for a given digital input query. The hamming distance which can be computed by TCAM is used after the binarization of data, while with limited accuracy. (b) KNN inference latency for each sample with Hamming distance or analog Hamming distance on CPU or CAM. The latency is averaged over 10 times on the 4 datasets. TCAM is a traditional 45 nm node 16 T CMOS. Compared with hamming distance, the analog hamming distance costs more time in CPU but can be efficiently accelerated by analog CAM (ACAM), about 108 times faster.
Extended Data Fig. 9 The electrical performance of MoS2 dual-gate flash memory array.
(a) The optical image 16x16 MoS2 dual-gate flash memory array, which can be used as an 8×16 analog CAM array with 256 MoS2 dual-gate flash memories (LCH/WCH = 0.5/10 µm). The scale bar is 200 µm. Inset is a zoomed-in image, showing two analog CAM cells with four MoS2 dual-gate flash memories. The scale bar is 10 µm. (b) ID-VG curves of the dual gate device at VD = 1 V, showing increased current ON/OFF ratio (~1010), ION, and steeper subthreshold slop (SS), indicating that the dual gate configuration can enhance electrostatic control, facilitate additional carrier accumulation, and improve the carrier transfer efficiency. (c) Statistics of readout current at VG = 3 V and VD = 1 V for 104 dual-gate and 586 back-gate MoS2 flash memories with LCH = 500 nm, showing a 1.5-time improvement of average readout current by dual-gate configuration. Statistical distribution of readout current at VD = 1 V and VG = 2 V for the fifty flash memories. Each box plot displays the 25% to 75% (box boundaries), median (central line), and mean (square symbol) of the data range. Whiskers extend to a full range (min to max). The symmetric distribution curve scales the full data range. (d) 10-time cycles-to-cycle test for ten programmed states with a programming voltage of 7 V ~ 12 V, showing a cycle-to-cycle uniformity. (e) The ten extracted Vth maintain distinct after over 1000 s cycles-to-cycle measurement.
Extended Data Fig. 10 Experimental demonstration of the search operations performance of one analog CAM cell with 3D-stacked complementary 2D flash memories.
(a) The schematic diagram of one analog CAM cell with 3D monolithic integration of complementary flash memories (N-type MoS2 and P-type WSe2). (b) The I_ML - V_DL curves of the analog CAM cell, showing a tunable match range. (c) The optical image of the 3D monolithic integration of complementary flash memories. Inset shows the circuit diagram. (d) Cross-sectional HAADF-STEM image, and (e) EDS mapping of the device.
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Gao, G., Wen, B., Yang, N. et al. Sb-contacted MoS2 flash memory for analogue in-memory searches. Nat. Nanotechnol. (2025). https://doi.org/10.1038/s41565-025-02089-7
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DOI: https://doi.org/10.1038/s41565-025-02089-7
