Extended Data Fig. 9: The electrical performance of MoS2 dual-gate flash memory array.
From: Sb-contacted MoS2 flash memory for analogue in-memory searches
(a) The optical image 16x16 MoS2 dual-gate flash memory array, which can be used as an 8×16 analog CAM array with 256 MoS2 dual-gate flash memories (LCH/WCH = 0.5/10 µm). The scale bar is 200 µm. Inset is a zoomed-in image, showing two analog CAM cells with four MoS2 dual-gate flash memories. The scale bar is 10 µm. (b) ID-VG curves of the dual gate device at VD = 1 V, showing increased current ON/OFF ratio (~1010), ION, and steeper subthreshold slop (SS), indicating that the dual gate configuration can enhance electrostatic control, facilitate additional carrier accumulation, and improve the carrier transfer efficiency. (c) Statistics of readout current at VG = 3 V and VD = 1 V for 104 dual-gate and 586 back-gate MoS2 flash memories with LCH = 500 nm, showing a 1.5-time improvement of average readout current by dual-gate configuration. Statistical distribution of readout current at VD = 1 V and VG = 2 V for the fifty flash memories. Each box plot displays the 25% to 75% (box boundaries), median (central line), and mean (square symbol) of the data range. Whiskers extend to a full range (min to max). The symmetric distribution curve scales the full data range. (d) 10-time cycles-to-cycle test for ten programmed states with a programming voltage of 7 V ~ 12 V, showing a cycle-to-cycle uniformity. (e) The ten extracted Vth maintain distinct after over 1000 s cycles-to-cycle measurement.
