Main

Quantum computation has promising potential for accelerating the solving of certain classes of computational problems compared with classical computation1,2. However, the inherent fragility of quantum systems poses a major challenge in implementing quantum computations on quantum devices. Fault-tolerant quantum computation (FTQC)3,4 uses quantum error-correcting codes to encode logical qubits and suppress errors, typically incurring a space overhead (the number of physical qubits per logical qubit) and a time overhead (the ratio of physical to logical circuit depth). Currently, two prominent schemes have been proposed for FTQC: one is a concatenated code scheme3,4,5,6, and the other is a quantum low-density parity-check (QLDPC) code scheme7,8,9,10,11,12,13,14,15,16,17. For both schemes, threshold theorems4,5,7,18,19,20,21,22,23,24,25 guarantee that the failure probability of the fault-tolerant simulation can be arbitrarily suppressed, provided that the physical error rate is below a certain threshold. Conventional FTQC schemes, using vanishing-rate codes such as those using surface codes9,10 or concatenated Steane codes5, incur polylogarithmic overheads in both space and time with respect to the size of the original quantum circuit.

In recent years, there have been notable advances towards achieving a constant space overhead by using non-vanishing-rate codes. Ref. 11 clarified the properties that non-vanishing-rate QLDPC codes must retain to achieve FTQC with constant space overhead, in combination with concatenated Steane codes. Subsequently, refs. 26,27 showed that quantum expander codes16,26,28 can serve as suitable QLDPC codes for this protocol. In this protocol, logical gates are implemented via gate teleportation using auxiliary states encoded in QLDPC codes3,29,30. The fault-tolerant preparation of these auxiliary states has been challenging without relying on the conventional protocol using concatenated Steane codes3,5. However, the conventional protocol incurs a growing space overhead3,5, which undermines complete gate parallelism when we need to maintain a constant space overhead. As a result, the existing analyses in refs. 11,26,27 require sequential gate implementation, leading to a polynomial increase in the time overhead of this protocol. More recently, ref. 6 resolved this bottleneck by developing a new constant-space-overhead protocol with complete gate parallelism based on concatenated quantum Hamming codes. However, even with this fully parallel execution of gates, the protocol only achieves quasi-polylogarithmic time overhead. Thus, it remains an open question whether it is possible to design an even faster constant-space-overhead protocol that achieves the polylogarithmic time overhead.

From a more fundamental perspective, this question involves a trade-off relation between space and time overhead in FTQC, originally raised in ref. 11 and partially addressed in ref. 6. On the one hand, conventional protocols that use vanishing-rate codes3,4,5,14, whether they are QLDPC codes or concatenated codes, incur polylogarithmic overheads in both space and time. On the other hand, the newer protocols using non-vanishing-rate codes achieve constant space overhead, but this improvement comes at the expense of increased time overhead. Remarkably, both QLDPC-code-based and concatenated-code-based approaches exhibit a similar pattern here as well, where reductions in space overhead have so far led to increases in time overheads beyond the conventional polylogarithmic scaling6,27. The essential focus here is not to propose a marginally improved protocol that outperforms existing ones in certain respects, but rather to address a more fundamental question: whether it is possible to overcome the barrier of super-polylogarithmic time overhead while maintaining constant space overhead.

Another fundamental issue is that the existing analyses of threshold theorems for protocols with QLDPC codes11,26,27,31 assume that classical computations are performed instantaneously on arbitrarily large scales, and before our work, the non-zero runtime of classical computations in implementing FTQC was explicitly taken into account only in the analysis of the threshold theorem for concatenated codes6. To fully analyse the overhead achievable in FTQC, it is essential to incorporate the waiting time for noninstantaneous classical computations into the analysis. Analysing overhead in FTQC must consider all possible bottlenecks, including the runtime of classical computation in executing FTQC (for example, decoding algorithms for error correction and gate teleportation), because the decoding runtime, which has often been considered negligible in theoretical analyses, can dominate the asymptotic scaling32. In fact, accounting for decoding delays in surface-code-based protocols not only increases the exponent in the polylogarithmic time overhead, but may potentially make FTQC infeasible due to severe slowdowns—an issue known as the backlog problem32. Such asymptotically non-negligible classical computations can also render the existence of a threshold non-trivial. In practice, even at current scales, classical computations have already become non-negligible bottlenecks, further underscoring the practical necessity of such comprehensive analyses33,34.

In this Article, we address these challenges and rigorously prove that a polylogarithmic time overhead can be achieved while maintaining a constant space overhead, even when fully accounting for non-zero classical computation times, using the non-vanishing-rate QLDPC codes. Our main theorem is informally stated as follows.

Theorem 1

Let \(\{{C}_{n}^{{\rm{org}}}\}\) be a sequence of original circuits indexed by an integer n. Each circuit \({C}_{n}^{{\rm{org}}}\) has width W(n) and depth D(n), where the size of \({C}_{n}^{{\rm{org}}}\) is polynomially bounded, that is, \(| {C}_{n}^{{\rm{org}}}| =\)\(O(W(n)D(n))=O({\rm{poly}}(n))\) as n → ∞. Then, for all target error ε > 0, there exists a threshold pth > 0 such that, if the physical error rate p is below the threshold, that is, p < pth, then there exists a sequence of fault-tolerant circuits \(\{{C}_{n}^{{\rm{FT}}}\}\) such that the classical output of \({C}_{n}^{{\rm{FT}}}\) is sampled from a probability distribution close to that of \({C}_{n}^{{\rm{org}}}\) in terms of total variation distance at most ε, and \({C}_{n}^{{\rm{FT}}}\) has a width WFT(n) and a depth DFT(n) satisfying

$$\begin{array}{rcl}\frac{{W}_{{\rm{FT}}}(n)}{W(n)}&=&O(1),\\ \frac{{D}_{{\rm{FT}}}(n)}{D(n)}&=&O\left({\rm{polylog}}\left(\frac{n}{\varepsilon }\right)\right),\end{array}$$
(1)

as n → ∞.

The formal statement and proof of this theorem, along with the necessary definitions, are provided in Supplementary Sections II and V, in particular in theorem 11 therein. Our analysis is based on standard assumptions in the previous studies on FTQC5,6,7,11,26 (Supplementary Section II). In particular, we assume no geometric locality constraint on two-qubit gates; a CNOT gate can be applied to an arbitrary pair of physical qubits in a single time step. This is motivated by platforms such as neutral atoms, trapped ions and optics, which may offer pathways to realizing such non-local interactions35,36,37,38,39,40,41,42,43,44. To prove theorem 1, we present and analyse a hybrid fault-tolerant protocol that combines concatenated Steane codes5 and non-vanishing-rate QLDPC codes with an efficient decoding algorithm, specifically quantum expander codes16, refining the previous analyses in refs. 11,26,27. Our analysis enables the polylogarithmic time overhead by increasing gate parallelism in the gate operations using gate teleportation, substantially improving the polynomial time overhead of the previous analyses in refs. 11,26,27, while still maintaining a constant space overhead.

Our analysis addresses and fixes a previously overlooked problem in the existing analyses11,26,27 of the threshold theorem for the QLDPC codes. In the analyses of FTQC, it is conventional to consider the local stochastic Pauli error model, where the correlated errors may occur across the entire fault-tolerant quantum circuit, as in refs. 11,26,27. For each code block of the QLDPC codes, the existing analyses in refs. 11,26,27 argue that the physical error rate of the codeword is suppressed after noisy syndrome measurements followed by quantum error correction using decoding algorithms, but this codeword state is on specific code blocks, that is, only in a small part of the entire fault-tolerant circuit on which the local stochastic Pauli error model is defined. This argument overlooks the correlations between this part of the circuit and the rest of the circuit surrounding this part, leaving the overall proof of the threshold theorem incomplete. To address this issue, we introduce a new method called partial circuit reduction. This method enables error analysis of the entire fault-tolerant circuit through the examination of individual gadgets on the code blocks of QLDPC codes. Our approach allows us to leverage the existing results from the decoding algorithms11,26,27 as a black box, so that we fully complete the proof of the threshold theorem for the constant-space-overhead protocol with the QLDPC codes. Furthermore, by combining this method with theoretical advances of the decoding algorithms in refs. 26,27, we show that it is indeed possible to achieve higher parallelization of the logical gates compared with the existing analyses in refs. 11,26,27, resulting in a polylogarithmic time overhead. These advances contribute to a fundamental understanding of the overhead and its space-time trade-off in FTQC and provide a robust foundation for realizing quantum computation.

We note that, in a concurrent work, another fault-tolerant protocol with constant space overhead and polylogarithmic time overhead45 has been proposed, relying on an approach substantially different from ours. The primary contribution of our work lies in the proof of the threshold theorem, which takes into account the non-zero runtime of classical computation.

Hybrid approach with QLDPC codes and concatenated codes

In our protocol, quantum expander codes, which are Calderbank–Shor–Steane low-density parity-check codes with a non-vanishing rate, serve as the registers that store and protect logical qubits46,47. Using the conventional notation [[N, K, D]] for the code parameters (N is the number of physical qubits, K is the number of logical qubits and D is the code distance), quantum expander codes16 exhibit parameters of \([[N,K={{\varTheta}}(N),D={{\varTheta}}(\sqrt{N})]]\), so the rate K/N remains positive as N → ∞. Together with the small-set-flip decoder, these codes suppress the probability of decoding failure, which may lead to logical error, exponentially in the code distance, as established in refs. 26,27. These properties make quantum expander codes well suited for high-capacity, robust quantum memory.

To realize a universal gate set that manipulates this QLDPC-encoded quantum memory, we use a hybrid approach involving concatenated Steane codes5,47,48 to prepare auxiliary states encoded by quantum expander codes in a fault-tolerant manner, enabling the logical gates via gate teleportation. The fault-tolerant protocol with concatenated Steane codes can be used to simulate arbitrary original quantum circuits, albeit with polylogarithmic overheads in both time and space5. In our hybrid approach, this concatenated Steane code protocol is crucially used to prepare logical auxiliary states that are encoded in the QLDPC code.

The fault-tolerant preparation of an auxiliary state, denoted by \(\left\vert \psi \right\rangle\), which is a physical state representing a codeword of a QLDPC code that encodes a target logical auxiliary state, can be understood intuitively as follows. While \(\left\vert \psi \right\rangle\) can be prepared by some non-fault-tolerant unitary circuit, such a circuit cannot be directly used for its fault-tolerant preparation. Instead, the idea is to first prepare \(\left\vert \psi \right\rangle\) as a logical state encoded in the concatenated Steane code. Because the well-established fault-tolerant protocol with the concatenated Steane code supports simulation of universal quantum computation, this Steane-encoded version of \(\left\vert \psi \right\rangle\) can be prepared with a sufficiently low logical error rate. We then convert this logical state into the physical state \(\left\vert \psi \right\rangle\) over the physical qubits, by decoding the concatenated Steane code. Roughly speaking, this step introduces errors on each physical qubit at the physical error rate, up to constant factors. This fact was implicitly used in the previous analysis of the constant-space-overhead protocol based on QLDPC codes11, and we provide a rigorous proof and explicit bound on this error rate in Supplementary Appendix A. Although each physical qubit may now suffer errors at the physical error rate, it is important to recall that \(\left\vert \psi \right\rangle\) is already encoded as a codeword of the QLDPC code. Therefore, we can transition to using the decoder of the QLDPC code to continue suppressing its decoding failure probability and protect the encoded logical state in \(\left\vert \psi \right\rangle\). Once these QLDPC-encoded auxiliary states are fault-tolerantly prepared, they enable the implementation of logical Clifford and non-Clifford gates on the QLDPC logical qubits via fault-tolerant gate teleportation3,29,30, thereby equipping our protocol with a universal set of logical operations.

Compilation procedure

The compilation process in our hybrid fault-tolerant protocol consists of two stages (see Fig. 1 and Supplementary Section III for details).

Fig. 1: Compilation procedure of our hybrid fault-tolerant protocol.
figure 1

The process involves two main stages. The aim of the first stage is to convert an original quantum circuit \({C}_{n}^{{\rm{org}}}\) to an intermediate circuit acting on registers, where each register is a collection of at most K qubits. The intermediate circuit is composed of a predetermined set of elementary operations, which includes a \({\left\vert 0\right\rangle }^{\otimes K}\)-state preparation, Clifford-state preparations, magic-state preparations, Pauli-gate operations, a CNOT-gate operation, a ZK-measurement operation, a Bell-measurement operation and a wait operation. The compilation begins with partitioning the qubits of the original circuit into registers. Then, \(\left\vert 0\right\rangle\)-state preparations in the original circuit are replaced by \({\left\vert 0\right\rangle }^{\otimes K}\)-state preparations, and Z-basis measurements are replaced by ZK-measurement operations. Clifford gates (for example, a tensor product of the Hadamard H gate) and non-Clifford gates (for example, a tensor product of T gates) in the original circuit are converted into a Clifford unitary UC acting on two registers and a non-Clifford unitary UT on a single register, respectively. To maintain constant space overhead, the number of the \({\left\vert 0\right\rangle }^{\otimes K}\)-state preparations, the UC gates, the UT gates and the ZK-measurement operations performed at a single time step is limited to \({\varTheta}(W(n)/{\rm{polylog}}(n/{\varepsilon}))\), where W(n) is the original circuit width. Following this, each of the UC gates and the UT gates is replaced by a sequence of elementary operations performing the corresponding teleportation with the aid of auxiliary registers, which is denoted as a UC-gate or a UT-gate abbreviation. The next stage is the compilation of this intermediate circuit into the fault-tolerant circuit \({C}_{n}^{{\rm{FT}}}\). This stage is achieved by replacing each elementary operation with a corresponding gadget, and an EC gadget is inserted between each pair of adjacent gadgets.

Full size image

First, an original quantum circuit is compiled into an intermediate circuit described as follows. An original circuit consists of initial state preparation, Clifford gates, non-Clifford gates and measurements. The qubits of the original circuit are partitioned into collections of at most K qubits each, called registers6. Here, K is chosen to match the number of logical qubits of the QLDPC code to be used, because each qubit in the intermediate circuit will eventually be regarded as a logical qubit of the code. For the compilation, we rewrite the original circuit using the following operations acting on registers: a \({\left\vert 0\right\rangle }^{\otimes K}\) -state preparation, Clifford unitaries UC acting on two registers, non-Clifford unitaries UT on a single register and a ZK measurement (Fig. 1). To achieve constant overhead, we restrict the number of the preparations, the measurements and the unitary gates executed in parallel, which is done by inserting the wait operations to delay part of the operations. Then, we regard each of the unitary gates as an abbreviation of a gate-teleportation circuit composed of elementary operations and equipped with ancillary registers. Here, the set of the elementary operations is composed of a \({\left\vert 0\right\rangle }^{\otimes K}\)-state preparation, Clifford-state preparations, magic-state preparations, Pauli-gate operations, a CNOT-gate operation, a ZK-measurement operation, a Bell-measurement operation and a wait operation. At this point, the original circuit has been converted to a circuit composed of the elementary operations, which we call the intermediate circuit (Fig. 1).

Next, this intermediate circuit is compiled into a fault-tolerant circuit. In this stage, each elementary operation within the intermediate circuit is replaced with its corresponding gadget, and each register is replaced with the QLDPC code block. Each gadget is a physical circuit designed to perform the logical operation acting on the logical qubits within a code block of the QLDPC code in a fault-tolerant way. As described above, the state-preparation gadget is fault-tolerantly constructed using the concatenated Steane code, while the other gadgets can be implemented transversally for quantum expander codes. Furthermore, an error-correction (EC) gadget acting on each code block is inserted between each pair of adjacent gadgets. Through this process, the final fault-tolerant circuit is constructed.

High parallelism to achieve polylogarithmic time overhead

A crucial feature of our protocol is its ability to achieve higher parallelism in executing logical gates compared with existing constant-space-overhead fault-tolerant protocols with QLDPC codes11,26,27, making it possible to achieve polylogarithmic time and constant space overhead simultaneously. In previous analyses11,26,27 for constant-overhead FTQC with QLDPC codes, logical gates could act simultaneously act on only O(W(n)/poly(n/ε)) logical qubits. This limitation naturally led to a polynomial time overhead.

Our protocol overcomes this bottleneck by providing a refined analysis of the required code size for quantum expander codes. These codes exhibit an exponential suppression of decoding failure probability as we increase the code distance. Indeed, this error suppression enables the use of a very small QLDPC code block size, scaling only polylogarithmically. The use of such small code blocks is important for our protocol; it reduces the resources required for the auxiliary states needed for gate teleportation. The QLDPC-encoded auxiliary states required for gate teleportation are prepared using a concatenated Steane code protocol. The fault-tolerant preparation using the concatenated Steane code itself incurs polylogarithmic space and time overheads. Implementation of each logical qubit of the QLDPC code thus requires a polylogarithmic number of physical qubits. Furthermore, each logical gate, implemented via these auxiliary logical states prepared using concatenated Steane codes, also introduces a polylogarithmic time overhead. This polylogarithmic requirement for the QLDPC code block size, in turn, enables the performance of more logical operations, that is, those on \(O(W(n)/{\rm{polylog}}(n/\varepsilon ))\) logical qubits, in parallel at each time step while maintaining the constant space overhead. This substantially increased parallelism in logical gate execution contributes to achieving a polylogarithmic time overhead. The detailed overhead analysis is presented in Supplementary Section V.

New techniques to complete the threshold theorem for FTQC with QLDPC codes

A key challenge in proving the threshold theorem for FTQC with QLDPC codes lies in consistently analysing errors across the entire fault-tolerant circuit, especially when individual code blocks are decoded locally. Existing analyses often focus on error suppression within a single QLDPC code block, overlooking correlations between the block and the rest of the circuit11,26,27, which is globally subject to a local stochastic Pauli error model11,26,27.

To address this fundamental issue, we introduce and utilize a technique called partial circuit reduction. The core motivation for this technique is to provide a systematic framework for analysing errors in a modular fashion. In our fault-tolerant circuit, each operation gadget is followed by EC gadgets for the associated code blocks, forming a circuit segment, which we call a rectangle. Instead of tackling the entire fault-tolerant circuit at once, we sequentially analyse errors in each rectangle. Partial circuit reduction allows us to formally replace a noisy rectangle in the fault-tolerant circuit with its ideally behaving, noiseless version, while appropriately updating the probability distribution of faulty locations in the subsequent, not-yet-analysed parts of the circuit. This step-by-step reduction is easy to use because it only requires analysis of a local segment at a time, while ensuring that the global statistics of fault occurrences continue to follow the same model with updated parameters. This method enables us to systematically manage error correlations and integrate established results from decoding algorithms26,27 as black-box components within a complete and rigorous proof of threshold existence. The detailed mathematical formulation of partial circuit reduction and its application in proving the threshold theorem are presented in Supplementary Section V.

Existence of threshold considering classical computation with non-negligible runtime

With all techniques described above, we prove the threshold theorem for our protocol. A fundamental challenge in theoretical FTQC analysis, often leading to oversimplification, is the reliance on the assumption that classical computation required in error correction and gate teleportation can be performed instantaneously, that is, in zero time26,27,49. In reality, these computations have a non-zero runtime that may grow as the size of original circuits becomes larger. The impact of this additional runtime is not limited to the time overhead. Because errors accumulate during the wait time for classical computation, they can potentially affect space overheads and even the existence of a fault-tolerant threshold.

Our analysis explicitly incorporates this non-zero runtime by inserting appropriate wait periods in the fault-tolerant circuit such that outcomes of classical computation can be used to choose on-demand operations. To establish a threshold under this realistic condition, we identify crucial properties for the decoding algorithm of the QLDPC codes to satisfy. These include: (1) the single-shot property, enabling error correction from a single round of potentially noisy syndrome measurements; (2) iterative execution, where each internal loop of the decoder completes in O(1) time with O(N) classical parallel processors; (3) exponential suppression of decoding failure probability with code distance; and (4) monotonic reduction of residual physical error rate with the number T of the internal loops when physical and syndrome error rates are below certain thresholds. We confirm that the small-set-flip decoder for the quantum expander code26,27 fulfils these requirements. These conditions ensure that the execution of the decoder within the EC gadget (that is, the wait time) can always be kept to a constant time, even if we carefully account for classical processing time. This has enabled us to rigorously prove the existence of a fault-tolerance threshold for our protocol without compromising overhead scalings. The detailed conditions for the decoder and the proof of the threshold theorem are provided in Supplementary Sections IV and V, respectively.

Conclusion and outlook

In this Article, we have presented a hybrid fault-tolerant protocol that combines concatenated codes for gate operations and non-vanishing-rate QLDPC codes (in particular, the quantum expander codes16,26,28) for quantum memory. These results contribute to a fundamental understanding of the overhead and its space-time trade-off required to realize FTQC. Unlike previous analyses that assumed instantaneous classical computations, our work explicitly accounts for non-zero-time classical computation times and their associated error accumulation. Incorporating classical runtime into the overhead analysis and establishing a threshold theorem under this setting not only offers a comprehensive understanding of overheads accounting for every possible bottleneck, but also provides a solid foundation for realizing FTQC. An encouraging aspect of our results is that polylogarithmic time overhead and constant space overhead can be achieved using well-established components: quantum expander codes and concatenated Steane codes. Both of these have been the focus of active experimental research in various physical architectures. Recent theoretical proposals indicate the feasibility of quantum expander codes in scalable systems such as neutral atoms and superconducting circuits42,43,44, while small-scale protocols with the Steane code have already begun to be demonstrated experimentally37,50,51. Our findings indicate a promising potential for low-overhead FTQC using the hybrid approach that combines non-vanishing-rate QLDPC codes and concatenated codes, in addition to relying solely on the code-concatenation approach as proposed in refs. 6,52. With regard to practical implementation, our results clarify the competing time overheads of these two constant-space-overhead approaches, highlighting the importance of a comprehensive investigation into the physical realizability of both approaches.