Abstract
Recent advances in quantum error correction in various hardware platforms have demonstrated operation near and beyond the threshold for fault-tolerant quantum computing. However, scaling up to achieve the exponential suppression of logical errors needed for fault tolerance remains challenging. Erasure qubits offer a path towards resource-efficient error correction, which enables the hardware-level detection of dominant error types. Single erasure qubits with dual-rail encoding in superconducting devices have demonstrated high coherence and low single-qubit gate errors with mid-circuit erasure detection. Here we demonstrate the generation of logical multi-qubit entanglement under error-biased protection using pairs of tunable transmons in a superconducting quantum processor. Each dual-rail qubit maintains millisecond-scale coherence times and logical single-qubit gate error rates on the order of 10−5 by using post-selection to mitigate erasure errors. We then demonstrate a logical \(\sqrt{{\rm{iSWAP}}}\) gate and the generation of a logical Bell state by engineering tunable couplings between the logical qubits. Building on this, we synthesize a logical controlled-NOT gate with a process fidelity of 98.1% at a 13% erasure rate, enabling the creation of a three-logical-qubit Greenberger–Horne–Zeilinger state with 93.9% fidelity.
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Source data are provided with this paper. Additional data relevant to this study are available from the corresponding authors upon reasonable request
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Acknowledgements
This work was supported by the Science, Technology and Innovation Commission of Shenzhen Municipality (grant number KQTD20210811090049034) (Y. Zhong), the National Natural Science Foundation of China (grant numbers 12174178 and 12404582) (Y. Zhong and X.L.), Shenzhen Science and Technology Program (grant number RCBS20231211090815032) (X.L.), Guangdong Provincial Project (grant number 2024QN11X158) (X.L.) and the Innovation Program for Quantum Science and Technology (grant number 2021ZD0301703) (Y. Zhong and S.L.).
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Y. Zhong conceived the experiment and supervised the project. X.L. performed the measurements and analysed the data. W.H. designed and tested the device. X.S. developed the field-programmable gate array program for the custom electronics built by Jiawei Zhang. All authors contributed to the experimental setup, discussions of the results and writing of the manuscript.
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Extended data
Extended Data Fig. 1 Calibration of accumulated phases during logical \(\sqrt{{\rm{iSWAP}}}\) gate.
a, Calibration of accumulated single qubit phase during \(\sqrt{{\rm{iSWAP}}}\) gate. The top panel is the pulse sequence and the bottom panel is the measured data. The measured data are the population of \({\left|00\right\rangle }_{{\rm{L}}}\) (\({\left|01\right\rangle }_{{\rm{L}}}\)) as a function of the rotation angle of the second π/2 pulse with the logical qubit first initialized to \({\left|00\right\rangle }_{{\rm{L}}}\) (\({\left|01\right\rangle }_{{\rm{L}}}\)). Solid lines are sinusoid fit. The arrows mark the determined calibrated phases. b, Calibration of the relative phase δ during \(\sqrt{{\rm{iSWAP}}}\) gate. The top panel is the pulse sequence and the bottom panel is the measured data. The measured data are the off-diagonal term of the density matrix, \({\rho }_{{\left|01\right\rangle }_{{\rm{L}}}{\left\langle 10\right|}_{{\rm{L}}}}\), as a function of the relative phase δ used in the four calibration pulses Rz(θi). Solid lines are sinusoid fit. The arrow marks the determined calibrated phase.
Extended Data Fig. 2 Process matrix of the logical CNOT gate.
The imaginary part of the process matrix χ for the logical CNOT gate.
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Huang, W., Sun, X., Zhang, J. et al. Logical multi-qubit entanglement with dual-rail superconducting qubits. Nat. Phys. (2026). https://doi.org/10.1038/s41567-026-03211-9
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DOI: https://doi.org/10.1038/s41567-026-03211-9
